LT3582 데이터 시트보기 (PDF) - Linear Technology

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LT3582

I2C Programmable Boost and Single Inductor Inverting DC/DC Converters with OTP

Linear Technology 

LT3582/LT3582-5/LT3582-12

PIN FUNCTIONS

CA (Pin 1): I2C Address Select Pin. Tie this pin to VIN to set

the 7-bit address to 0110 001. Tie to GND for 1000 101.

VOUTN (Pin 2): Negative Output Voltage Pin. When the con-

verter is operating, this pin is regulated to the programmed

negative output voltage. Place a ceramic capacitor from

this pin to GND.

SWN (Pins 3 & 4): Negative switching node for the In-

verting converter. This is the drain of the internal PMOS

power switch. Connect one end of the Inverting inductor

to these pins. Keep the trace area on these pins as small

as possible.

VIN (Pin 5): Input supply pin and source of the PMOS

power switch. This pin must be bypassed locally with a

ceramic capacitor. The operating voltage range of this pin

is 2.55V to 5.5V.

RAMPN (Pin 6): Soft start ramp pin for the Inverting

converter. Place a capacitor from this pin to GND. A

programmable current of 1μA - 8μA (LT3582) or 1μA

(LT3582-5/LT3582-12) charges this pin during startup,

limiting the ramp rate of VOUTN. This pin is discharged to

GND during shutdown.

RAMPP (Pin 7): Soft start ramp pin for the Boost converter.

Place a capacitor from this pin to GND. A programmable

current of 1μA - 8μA (LT3582) or 1μA (LT3582-5/LT3582-12)

charges this pin during startup, limiting the ramp rate of

VOUTP. This pin is discharged to GND in shutdown.

SHDN (Pin 8): Shutdown Pin. Drive this pin to 1.1V or

higher to enable the part. Drive to 0.3V or lower to shut

down. Includes an integrated 222k pulldown resistor.

VOUTP (Pin 9): Output of the Boost converter output

disconnect circuit. A ceramic capacitor should be placed

from this node to GND. During shutdown, this pin is

disconnected from the Boost network which allows this

pin to discharge to GND, assuming a load is present to

discharge the capacitance.

CAPP (Pins 10 & 11): Connect the Boost output capacitor

from these pins to GND. During shutdown, the voltage on

these pins will remain close to the input voltage due to

the path through the Boost inductor and Schottky. During

normal operation, CAPP will be boosted slightly higher

than the programmed output voltage.

SWP (Pin 12): Positive switching node for the Boost

converter. This is the drain of the internal NMOS power

switch. Connect one end of the Boost inductor to this pin.

Keep the trace area on this pin as small as possible.

GND (Pin 13): Ground Pin. Tie to a local ground plane.

Proper PCB layout is required to achieve advertised

performance; see Applications Information section for

more information.

VPP (Pin 14): Programming Voltage Pin. Drive this pin

to 13-15V when programming the OTP memory. Float

otherwise. A bypass capacitor should be placed from

this node to GND if VPP is used for programming. If VPP

falls below 13V during OTP programming, an internal

FAULT bit, which can be read through the I2C interface,

can be set high.

SDA (Pin 15): I2C Bidirectional Data Pin. Tie to GND or

VIN if unused.

SCL (Pin 16): I2C Clock Pin. Tie to GND or VIN if

unused.

Exposed Pad (Pin 17): Ground Pin. Tie to a local ground

plane. Proper PCB layout is required to achieve advertised

performance; see Applications Information section for

more information.

3582512f

8

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