LT3587 데이터 시트보기 (PDF) - Linear Technology

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LT3587

High Voltage Monolithic Inverter and Dual Boost

Linear Technology 

LT3587

OPERATION

All three channels of the LT3587 use a constant frequency,

current mode control scheme to provide voltage and/or

current regulation at the output. Operation can be best un-

derstood by referring to the Block Diagram in Figure 1.

If EN/SS1 is pulled higher than 200mV, the bandgap refer-

ence, the start-up bias and the oscillator are turned on. At

the start of each oscillator cycle, the SR latch X1 is set,

which turns on the power switch Q1. A voltage proportional

to the switch current is added to a stabilizing ramp and

the resulting sum is fed into the positive terminal of the

PWM comparator A3. When this voltage exceeds the level

at the negative input of A3, the SR latch X1 is reset, turning

off the power switch Q1. The level at the negative input

of A3 is set by the error amplifier A1, which is simply an

amplified version of the difference between the reference

voltage of 1.22V and the feedback voltage. In this manner,

the error amplifier sets the correct peak switch current

level to keep the output voltage in regulation. If the error

amplifier output increases, more current is delivered to

the output; if it decreases, less current is delivered.

The second channel is an inverting converter. This channel

is also enabled through the EN/SS1 pin. The basic opera-

tion of this second channel is the same as the positive

channel. The SR latch X2 is also set at the start of each

oscillator cycle. The power switch Q2 is turned on at the

same time as Q1. Q2 turns off based on its own feedback

loop, which consists of error amplifier A2 and PWM

comparator A4. The reference voltage of this negative

channel is ground.

Voltage clamps (not shown) on the output of the error

amplifiers A1 and A2 enforce current limit on Q1 and Q2

respectively.

Similar to the first channel, the third channel is also a

positive boost regulator. If EN/SS3 is pulled higher than

200mV, the bandgap reference, the start-up bias and the

oscillators are also turned on. The SR latch X3 is set at

the start of each oscillator cycle which turns on the power

switch Q3. Q3 turns off based on its own feedback loop,

which consists of error amplifier A5 and PWM comparator

A6. The level at the negative input of A6 is set by the error

amplifier A5, and is an amplified version of the difference

between the reference voltage of 0.8V and the maximum

of the two feedback voltages at VFB3 and IFB3. A separate

comparator (not shown) sets the maximum current limit

on Q3.

The IFB3 pin is pulled up internally with a current that

is (1/200) times the load current out of the VOUT3 pin.

Therefore, an external resistor connected from this pin

to ground generates a feedback voltage proportional to

the VOUT3 output load current at the IFB3 pin. When the

voltage at VFB3 is higher than the voltage at IFB3, the third

channel regulates to the feedback voltage at VFB3, which in

normal application is a divided down voltage from VOUT3.

In this state, the third channel behaves as a boost voltage

regulator. On the other hand if the voltage at IFB3 is higher,

the third channel regulates to the feedback voltage at IFB3,

which therefore regulates the VOUT3 output load current to

a particular value. In this state, the third channel behaves

as a boost current regulator.

PMOS M1 is used as an output disconnect pass transistor

for the first channel. M1 disconnects the load (VOUT1) from

the input as long as the voltage between CAP1 and VIN

is less than 2.5V (typical) and the voltage between CAP1

and VOUT1 is less than 10V (typ). Similarly, PMOS M3 is

used as an output disconnect pass transistor for the third

channel. M3 disconnects the load (VOUT3) from the input

when the third channel is in shutdown (EN/SS3 voltage

is lower than 200mV) and the voltage between CAP3 and

VOUT3 is less than 10V (typical).

3587fc

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