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LT3748

100V Isolated Flyback Controller

Linear Technology 

LT3748

Applications Information

Minimum Primary Inductance Requirements

Output Power

The LT3748 obtains output voltage information from the

external MOSFET drain voltage when the secondary winding

conducts current. The sampling circuitry needs a minimum

of 400ns to settle and sample the output voltage while the

MOSFET switch is off. This required settle and sample

time is controlled by external components independent of

the minimum off-time of the GATE pin as specified in the

Electrical Characteristics table. The electrical specification

minimum off-time is based on an internal timer and acts

as a maximum frequency clamp. The following equation

gives the minimum value for primary-side magnetizing

inductance:

( ) LPRI ≥

VOUT + VF(DIODE) • RSENSE • tSETTLE(MIN) • NPS

VSENSE(MIN)

VSENSE(MIN) = 15mV

tSETTLE(MIN) = 400ns

NPS = Ratio of primary windings to secondary windings

In addition to the primary inductance requirement for

minimum settling and sampling time, the LT3748 has

internal circuit constraints that prevent it from setting the

GATE node high for shorter than approximately 250ns.

If the inductor current exceeds the desired current limit

during that time oscillation may occur at the output as

the current control loop will lose its ability to regulate.

Therefore, the following equation relating to maximum

input voltage must also be followed in selecting primary-

side magnetizing inductance:

LPRI

≥

VIN(MAX) • RSENSE • tON(MIN)

VSENSE(MIN)

Because the MOSFET power switch is located outside the

LT3748, the maximum output power is primarily limited

by external components. Output power limitations can

be separated into three categories—voltage limitations,

current limitations and thermal limitations.

The voltage limitations in a flyback design are primar-

ily the MOSFET switch VDS(MAX) and the output diode

reverse-bias rating. Increasing the voltage rating of either

component will typically decrease application efficiency if

all else is equal and the voltage requirements on each of

those components will be directly related to the windings

ratio of the transformer, the input and output voltages

and the use of any additional snubbing components.

The MOSFET VDS(MAX) must theoretically be higher than

VIN(MAX) + (VOUT • NPS) and the output diode reverse bias

must be higher than VOUT + (VIN(MAX)/NPS), though leak-

age inductance spikes on both the drain of the MOSFET

and the anode of the output diode may more than double

that requirement (see section on leakage inductance for

more details on snubbers). Figure 1 illustrates the effect

on available output power for several MOSFET voltage

ratings while continuously maximizing windings ratio

for input voltage with a fixed MOSFET current limit and

output voltage. Increasing the MOSFET rating increases

the possible windings ratio and or maximum input voltage

and can increase the available output power for a given

application. Both figures assume no leakage inductance

and high efficiency.

50

VDS = 200V

VDS = 150V

40

tON(MIN) = 250ns

30

The last constraint on minimum inductance value would

relate to minimum full-load operating frequency, fSW(MIN),

and is derived from fSW = 1/(tON + tOFF):

LPRI ≤ VIN(MIN) • (VOUT + VF(DIODE)) • NPS/(fSW(MIN) • ILIM •

((VOUT + VF(DIODE)) • NPS + VIN(MIN)))

The minimum operating frequency may be lower than

the calculated number due to delays in detecting current

limit and detecting boundary mode that are specific to

each application.

VDS = 100V

20

10

0

0

20

40

60

80 100

INPUT VOLTAGE (V)

3748 F01

Figure 1. Maximum Output Power at 12VOUT with a

3A ILIM and Maximum VDS = 100V, 150V, 200V

3748fb

For more information www.linear.com/LT3748

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