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LT3800

High-Voltage Synchronous Current Mode Step-Down Controller

Linear Technology 

LT3800

PI FU CTIO S

and reverse-current inhibit functions are enabled. When

the pin voltage is above 0.5V, Burst Mode operation is

disabled, but reverse-current inhibit operation is main-

tained. DC/DC converters operating with reverse-current

inhibit operation (BURST_EN = VFB) have a 1mA minimum

load requirement. Reverse-current inhibit is disabled when

the pin voltage is above 2.5V. This pin is typically shorted

to ground to enable Burst Mode operation and reverse-

current inhibit, shorted to VFB to disable Burst Mode

operation while enabling reverse-current inhibit, and con-

nected to VCC pin to disable both functions. See Applica-

tions Information section.

VFB (Pin 6): Error Amplifier Inverting Input. The

noninverting input of the error amplifier is connected to an

internal 1.231V reference. Desired converter output volt-

age (VOUT) is programmed by connecting a resistive

divider from the converter output to the VFB pin. Values for

the resistor connected from VOUT to VFB (R2) and the

resistor connected from VFB to ground (R1) can be calcu-

lated via the following relationship:

R2

=

R1•

⎛⎝⎜

VOUT

1.231

–

1⎞⎠⎟

The VFB pin input bias current is 25nA, so use of extremely

high value feedback resistors could cause a converter

output that is slightly higher than expected. Bias current

error at the output can be estimated as:

∆VOUT(BIAS) = 25nA • R2

VC (Pin 7): Error Amplifier Output. The voltage on the VC

pin corresponds to the maximum (peak) switch current

per oscillator cycle. The error amplifier is typically config-

ured as an integrator by connecting an RC network from

this pin to ground. This network creates the dominant pole

for the converter voltage regulation feedback loop. Spe-

cific integrator characteristics can be configured to opti-

mize transient response. Connecting a 100pF or greater

high frequency bypass capacitor from this pin to ground

is also recommended. When Burst Mode operation is

enabled (see Pin 5 description), an internal low impedance

clamp on the VC pin is set at 100mV below the burst

threshold, which limits the negative excursion of the pin

voltage. Therefore, this pin cannot be pulled low with a

low-impedance source. If the VC pin must be externally

manipulated, do so through a 1kΩ series resistance.

SENSE– (Pin 8): Negative Input for Current Sense Ampli-

fier. Sensed inductor current limit set at ±150mV across

SENSE inputs.

SENSE+ (Pin 9): Positive Input for Current Sense Ampli-

fier. Sensed inductor current limit set at ±150mV across

SENSE inputs.

PGND (Pin 10): High Current Ground Reference for Syn-

chronous Switch. Current path from pin to negative termi-

nal of VCC decoupling capacitor must not corrupt SGND.

BG (Pin 11): Synchronous Switch Gate Drive Output.

VCC (Pin 12): Internal Regulator Output. Most IC func-

tions are powered from this pin. Driving this pin from an

external source reduces VIN pin current to 20µA. This pin

is decoupled with a low ESR 1µF capacitor to PGND.

In shutdown mode, this pin sinks 20µA until the pin

voltage is discharged to 0V. See Typical Performance

Characteristics.

NC (Pin 13): No Connection.

SW (Pin 14): Reference for VBOOST Supply and High

Current Return for Bootstrapped Switch.

TG (Pin 15): Bootstrapped Switch Gate Drive Output.

BOOST (Pin 16): Bootstrapped Supply – Maximum Oper-

ating Voltage (Ground Referred) to 75V. This pin is

decoupled with a low ESR 1µF capacitor to pin SW. The

voltage on the decoupling capacitor is refreshed through

a rectifier from either VCC or an external source.

Exposed Package Backside (SGND) (Pin 17): Low Noise

Ground Reference. SGND connection is made through the

exposed lead frame on back of TSSOP package which

must be soldered to the PCB ground.

3800fb

6

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