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LT3845

High Voltage Synchronous Current Mode Step-Down Controller with Adjustable Operating Frequency

Linear Technology 

LT3845

PIN FUNCTIONS

BG: The BG pin is the gate drive for the bottom N-channel

MOSFET. Since very fast high currents are driven from

this pin, connect it to the gate of the power MOSFET

with a short and wide, typically 0.02" width, PCB trace to

minimize inductance.

BOOST: The BOOST pin is the supply for the bootstrapped

gate drive and is externally connected to a low ESR ceramic

boost capacitor referenced to SW pin. The recommended

value of the BOOST capacitor, CBOOST, is at least 50 times

greater than the total gate capacitance of the topside MOSFET.

In most applications 0.1μF is adequate. The maximum volt-

age that this pin sees is VIN + VCC, ground referred.

BURST_EN: Burst Mode Operation Enable Pin. This pin

also controls reverse-current inhibit mode of operation.

When the pin voltage is below 0.5V, Burst Mode operation

and reverse-current inhibit functions are enabled. When

the pin voltage is above 0.5V, Burst Mode operation is dis-

abled, but reverse-current inhibit operation is maintained.

In this mode of operation (BURST_EN = VFB) there is a

1mA minimum load requirement. Reverse-current inhibit

is disabled when the pin voltage is above 2.5V. This pin is

typically shorted to ground to enable Burst Mode operation

and reverse-current inhibit, shorted to VFB to disable Burst

Mode operation while enabling reverse-current inhibit,

and connected to VCC pin to disable both functions. See

Applications Information section.

CSS: The soft-start pin is used to program the supply soft-

start function. Use the following formula to calculate CSS

for a given output voltage slew rate:

CSS = 2μA(tSS/1.231V)

The pin should be left unconnected when not using the

soft-start function.

fSET: The fSET pin programs the oscillator frequency with an

external resistor, RSET. The resistor is required even when

supplying external sync clock signal. See the Applications

Information section for resistor value selection details.

PGND: The PGND pin is the high-current ground reference

for internal low side switch driver and the VCC regulator

circuit. Connect the pin directly to the negative terminal of

the VCC decoupling capacitor. See the Application Informa-

tion section for helpful hints on PCB layout of grounds.

SENSE–: The SENSE– pin is the negative input for the

current sense amplifier and is connected to the VOUT

side of the sense resistor for step-down applications. The

sensed inductor current limit is set to ±100mV across the

SENSE inputs.

SENSE+: The SENSE+ pin is the positive input for the

current sense amplifier and is connected to the inductor

side of the sense resistor for step-down applications. The

sensed inductor current limit is set to ±100mV across the

SENSE inputs.

SGND: The SGND pin is the low noise ground reference.

It should be connected to the –VOUT side of the output

capacitors. Careful layout of the PCB is necessary to keep

high currents away from this SGND connection. See the

Application Information section for helpful hints on PCB

layout of grounds.

SHDN: The SHDN pin has a precision IC enable threshold

of 1.35V (rising) with 120mV of hysteresis. It is used to

implement an undervoltage lockout (UVLO) circuit. See

Application Information section for implementing a UVLO

function. When the SHDN pin is pulled below a transistor

VBE (0.7V), a low current shutdown mode is entered, all

internal circuitry is disabled and the VIN supply current

is reduced to approximately 9μA. Typical pin input bias

current is <10nA and the pin is internally clamped to 6V.

If the function is not used, this pin may be tied to VIN

through a high value resistor.

SW: Reference for VBOOST Supply and High Current Return

for Bootstrapped Switch.

SYNC: The Sync pin provides an external clock input for

synchronization of the internal oscillator. RSET is set such

that the internal oscillator frequency is 10% to 25% below

the external clock frequency. If unused the Sync pin is

connected to SGND. For more information see “Oscillator

Sync” in the Application Information section of this data

sheet. Sync pin not available in PDIP package.

3845fd

7

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