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LT3992

Monolithic Dual Tracking 3A Step-Down Switching Regulator

Linear Technology 

LT3992

Block Diagram

VIN1

SHDN1

1.32V +

–

VIN1

CHANNEL 1

THERMAL

SHUTDOWN

DROPOUT

ENHANCEMENT

BST1

–

S PRE

Q

DRIVER

CIRCUITRY

SW1

2.5V

+

R

D1

12µA

SS1

PRE

–

S

Q

IND1

+

R

110mV

VOUT1

VC1

2.5V

ILIM1

12µA

RLIM

SLOPE

2.5V

COMPENSATION

R1

FB1

CMPI1

R2

0.806V

0.72V +

–

CMPO1

12µA

RT/SYNC

R3

2.5V

CLK1

VIN1 +

INTERNAL

2.5V

TJ

REGULATOR

DIV

12µA

OSCILLATOR MASTER CLOCK

AND AGC

CLK2 TO CHANNEL 2

2.9V –

AND

REFERENCES

CLKOUT

GND

RDIV

3992 F01

Figure 1. LT3992 Block Diagram

The LT3992 is a dual channel, constant frequency, current

mode buck converter with internal 4.6A switches. Each

channel can be independently controlled with the exception

that VIN1 must be above the typically 2.9V undervoltage

lockout threshold to power the common internal regulator,

oscillator and thermometer circuitry.

If the SHDN1 pin is taken below its 1.32V threshold the

LT3992 will be placed in a low quiescent current mode. In this

mode the LT3992 typically draws 6µA from VIN1 and <1µA

from VIN2. When the SHDN pin is driven above 1.32V, the

internal bias circuits turn on generating an internal regulated

voltage, 0.806VFB, 12µA RT/SYNC, DIV and ILIM current

references, and a POR signal which sets the soft-start latch.

Once the internal reference reaches its regulation point,

the internal oscillator will start generating a master clock

signal for the two regulators at a frequency determined by

the voltage present at the RT/SYNC pin. The channel 1 clock

is then divided by 1, 2, 4 or 8 depending on the voltage

present at the DIV pin. Channel 2’s clock runs at the master

clock frequency with a 180° phase shift from channel 1.

Alternatively, if a synchronization signal is detected by

the LT3992 the RT/SYNC pin, the master clock will be

generated at the incoming frequency on the rising edge

of the synchronization pulse with channel 1 in phase with

the synchronization signal. Frequency division and phase

remains the same as the internally generated master clock.

In addition, the internal slope compensation will be au-

tomatically adjusted to prevent subharmonic oscillation

during synchronization. In either mode of oscillator op-

eration, a square wave with the master clock frequency,

synchronized to channel 1 is present at the CLKOUT pin.

The two regulators are constant frequency, current mode

step-down converters. Current mode regulators are con-

trolled by an internal clock and two feedback loops that

3992fa

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For more information www.linear.com/LT3992

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