LT5526EUF 데이터 시트보기 (PDF) - Linear Technology
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LT5526EUF Datasheet PDF : 16 Pages
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LT5526
APPLICATIO S I FOR ATIO
The purpose of L5 is to provide a DC return path for Pin 3.
(Another possible placement for L5 would be across Pins
2 and 3, thus using L1 as part of the DC return path.) The
inductance and resonant frequency of L5 should be large
enough that they don’t significantly affect the input imped-
ance and performance of the balun. Either multilayer or
wire-wound inductors may be used.
The impact of L5 on input matching can be reduced by
adding a capacitor in parallel with it. In this case, the
capacitor value should be the same as C7 and C9, while L5
should have the same value as L1 and L4.
Table 2. Component Values for Lumped Balun on RF Input
FREQUENCY
(MHz)
L (nH)
C (pF)
BANDWIDTH
L5 (nH)
(MHz)
240
27
18
100
100
380
15
10
100
130
680
6.8
4.7
47
215
900
6.8
3.9
18
230
1100
3.9
2.7
15
230
External 100pF DC blocking capacitors provide a broad-
band match from about 110MHz to 2.7GHz, as shown in
the plot of return loss vs frequency in Figure 8. The LO
input match can be improved at lower frequencies by
increasing the values of C5 and C6.
0
–5
–10
–15
–20
–25
–30
0
500 1000 1500 2000 2500
FREQUENCY (MHz)
5526 F08
Figure 8. Typical LO Input Return Loss
with 100pF DC Blocking Capacitors
LO Input Port
The LO buffer amplifier consists of high speed limiting
differential amplifiers designed to drive the mixer core for
high linearity. The LO+ and LO– pins are designed for single-
ended drive, though differential drive can be used if de-
sired. The LO input is internally matched to 50Ω; however,
external DC blocking capacitors are required because the
LO pins are internally biased to approximately 1.7V DC. A
simplified schematic for the LO input is shown in Figure 7.
C5
100pF
LO–
14
LT5526
C6
VCC
50Ω
100pF
LOIN
50Ω
LO+
15
5526 F07
Figure 7. LO Input Schematic
Table 3. Single-Ended LO Input Impedance
FREQUENCY
(MHz)
INPUT
IMPEDANCE
REFLECTION COEFFICIENT
MAG
ANGLE
400
63.4 – j12.0
0.158
–35.8
600
61.6 – j8.38
0.128
–31.5
800
61.8 – j6.86
0.122
–26.6
1000
62.4 – j7.09
0.127
–26.1
1200
62.8 – j8.32
0.135
–28.8
1400
62.6 – j10.3
0.144
–34.0
1600
61.9 – j12.6
0.154
–40.3
1800
60.5 – j14.4
0.160
–46.2
IF Output Port
A simplified schematic of the IF output circuit is shown in
Figure 9. The output pins, IF+ and IF–, are internally
connected to the collectors of the mixer switching transis-
tors. Both pins must be biased at the supply voltage, which
can be applied through the center-tap of a transformer or
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