LTC1290(Rev_C) 데이터 시트보기 (PDF) - Linear Technology
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LTC1290 Datasheet PDF : 28 Pages
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LTC1290
APPLICATI S I FOR ATIO
The LTC1290 is a data acquisition component which
contains the following functional blocks:
1. 12-bit successive approximation capacitive A/D
converter
2. Analog multiplexer (MUX)
3. Sample-and-hold (S/H)
4. Synchronous, full duplex serial interface
5. Control and timing logic
DIGITAL CONSIDERATIONS
Serial Interface
The LTC1290 communicates with microprocessors and
other external circuitry via a synchronous, full duplex,
four-wire serial interface (see Operating Sequence). The
shift clock (SCLK) synchronizes the data transfer with
each bit being transmitted on the falling SCLK edge and
captured on the rising SCLK edge in both transmitting and
receiving systems. The data is transmitted and received
simultaneously (full duplex).
Data transfer is initiated by a falling chip select (CS) signal.
After the falling CS is recognized, an 8-bit input word is
shifted into the DIN input which configures the LTC1290
for the next conversion. Simultaneously, the result of the
previous conversion is output on the DOUT line. At the end
of the data exchange the requested conversion begins and
CS should be brought high. After tCONV, the conversion is
complete and the results will be available on the next data
transfer cycle. As shown below, the result of a conversion
is delayed by one CS cycle from the input word requesting
it.
DIN DIN WORD 1
DIN WORD 2
DIN WORD 3
DOUT DOUT WORD 0
DOUT WORD 1
DOUT WORD 2
DATA
TRANSFER
tCONV
A/D
CONVERSION
DATA
TRANSFER
tCONV
A/D
CONVERSION
LTC1290 • AI01
Input Data Word
The LTC1290 8-bit data word is clocked into the DIN input
on the first eight rising SCLK edges after chip select is
recognized. Further inputs on the DIN pin are then ignored
until the next CS cycle. The eight bits of the input word are
defined as follows:
UNIPOLAR/
BIPOLAR
WORD
LENGTH
SGL/
DIFF
ODD/ SELECT SELECT
SIGN
1
0
UNI
MSBF
WL1
WL0
MUX ADDRESS
MSB-FIRST/
LSB-FIRST
LTC1290 • AI02
SCLK
CS
DIN
DOUT
Operating Sequence
(Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length)
tCYC
1 2 3 4 5 6 7 8 9 10 11 12
tSMPL
DON’T CARE
tCONV
SHIFT CONFIGURATION
WORD IN
DON’T CARE
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
(SB)
SHIFT A/D RESULT OUT AND
NEW CONFIGURATION WORD IN
LTC1290 • AI03
9
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