LTC1408IUH 데이터 시트보기 (PDF) - Linear Technology
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LTC1408IUH Datasheet PDF : 20 Pages
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LTC1408
PI FU CTIO S
CONV (Pin 30): Convert Start. Holds the six analog input
signals and starts the conversion on the rising edge. Two
pulses with SCK in fixed high or fixed low state starts Nap
mode. Four or more pulses with SCK in fixed high or fixed
low state starts Sleep mode.
DGND (Pin 31): Digital Ground. This ground pin must be
tied directly to the solid ground plane. Digital input signal
currents flow through this pin.
SCK (Pin 32): External Clock Input. Advances the conver-
sion process and sequences the output data at SD0 (Pin1)
on the rising edge. One or more pulses wake from sleep
or nap power saving modes. 16 clock cycles are needed
for each of the channels that are activated by SELx (Pins
26, 27, 28), up to a total of 96 clock cycles needed to
convert and read out all 6 channels.
EXPOSED PAD (Pin 33): GND. Must be tied directly to the
solid ground plane.
BLOCK DIAGRA
0.1µF
CH0+
CH0–
CH1+
CH1–
CH2+
CH2–
CH3+
CH3–
CH4+
CH4–
CH5+
CH5–
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
+
S&H
–
+
S&H
–
+
S&H
–
+
S&H
–
+
S&H
–
+
S&H
–
10µF
3V
VCC
VDD
24
25
14-BIT LATCH 0
14-BIT LATCH 1
MUX
600ksps
14-BIT ADC
14-BIT LATCH 2
14-BIT LATCH 3
14-BIT LATCH 4
14-BIT LATCH 5
TIMING
LOGIC
LTC1408
THREE-
STATE
SERIAL
OUTPUT
PORT
OVDD
3V
3
SD0
1
OGND
2
0.1µF
30 CONV
32 SCK
2.5V
REFERENCE
EXPOSED PAD
33
GND
VREF
22
23 29
10µF
BIP
26 27 28
SEL2 SEL1 SEL0
31
DGND
1408 BD
1408fa
9
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