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LTC1741IFW

12-Bit, 65Msps Low Noise ADC

Linear Technology 

LTC1741

APPLICATIO S I FOR ATIO

CONVERTER OPERATION

The LTC1741 is a CMOS pipelined multistep converter.

The converter has four pipelined ADC stages; a sampled

analog input will result in a digitized value five cycles later,

see the Timing Diagram section. The analog input is

differential for improved common mode noise immunity

and to maximize the input range. Additionally, the differen-

tial input drive will reduce even order harmonics of the

sample-and-hold circuit. The encode input is also

differential for improved common mode noise immunity.

The LTC1741 has two phases of operation, determined by

the state of the differential ENC/ENC input pins. For brev-

ity, the text will refer to ENC greater than ENC as ENC high

and ENC less than ENC as ENC low.

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC and an interstage residue amplifier.

In operation, the ADC quantizes the input to the stage and

the quantized value is subtracted from the input by the

DAC to produce a residue. The residue is amplified and

output by the residue amplifier. Successive stages operate

out of phase so that when the odd stages are outputting

their residue, the even stages are acquiring that residue

and visa versa.

When ENC is low, the analog input is sampled differentially

directly onto the input sample-and-hold capacitors, inside

the “Input S/H” shown in the block diagram. At the instant

that ENC transitions from low to high, the sampled input

is held. While ENC is high, the held input voltage is

buffered by the S/H amplifier which drives the first pipelined

ADC stage. The first stage acquires the output of the S/H

during this high phase of ENC. When ENC goes back low,

the first stage produces its residue which is acquired by

the second stage. At the same time, the input S/H goes

back to acquiring the analog input. When ENC goes back

high, the second stage produces its residue which is

acquired by the third stage. An identical process is re-

peated for the third stage, resulting in a third stage residue

that is sent to the fourth stage ADC for final evaluation.

Each ADC stage following the first has additional range to

accommodate flash and amplifier offset errors. Results

from all of the ADC stages are digitally synchronized such

that the results can be properly combined in the correction

logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC1741

CMOS differential sample-and-hold. The differential ana-

log inputs are sampled directly onto sampling capacitors

(CSAMPLE) through CMOS transmission gates. This direct

capacitor sampling results in lowest possible noise for a

given sampling capacitor size. The capacitors shown

attached to each input (CPARASITIC) are the summation of

all other capacitance associated with each input.

During the sample phase when ENC/ENC is low, the

transmission gate connects the analog inputs to the sam-

pling capacitors and they charge to, and track the differen-

tial input voltage. When ENC/ENC transitions from low to

high the sampled input voltage is held on the sampling

capacitors. During the hold phase when ENC/ENC is high

the sampling capacitors are disconnected from the input

and the held voltage is passed to the ADC core for

processing. As ENC/ENC transitions from high to low the

inputs are reconnected to the sampling capacitors to

acquire a new sample. Since the sampling capacitors still

hold the previous sample, a charging glitch proportional to

the change in voltage between samples will be seen at this

LTC1741 VDD

CPARASITIC

AIN+

4pF

VDD

CPARASITIC

AIN–

4pF

5V

CSAMPLE

4pF

CSAMPLE

4pF

BIAS

2V

6k

ENC

ENC

6k

2V

Figure 2. Equivalent Input Circuit

1741 F02

1741f

11

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