LTC1852I 데이터 시트보기 (PDF) - Linear Technology
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LTC1852I Datasheet PDF : 24 Pages
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LTC1852/LTC1853
PIN FUNCTIONS
CH0 to CH7 (Pins 1 to 8): Analog Input Pins. Input pins can
be used single ended relative to the analog input common
pin or differentially in pairs (CH0 and CH1, CH2 and CH3,
CH4 and CH5, CH6 and CH7).
COM (Pin 9): Analog Input Common Pin. For single-ended
operation (DIFF = 0), COM is the “–” analog input. COM
is disabled when DIFF is high.
REFOUT (Pin 10): Internal 2.5V Reference Output. Bypass
to analog ground plane with 1μF.
REFIN (Pin 11): Reference Mode Select/Reference Buffer
Input. REFIN selects the reference mode and acts as the
reference buffer input. REFIN tied to ground (Logic 0) will
produce 2.048V on the REFCOMP pin. REFIN tied to the
positive supply (Logic 1) disables the reference buffer
to allow REFCOMP to be driven externally. For voltages
between 1V and 2.6V, the reference buffer produces an
output voltage on the REFCOMP pin equal to 1.6384 times
the voltage on REFIN (4.096V on REFCOMP for a 2.5V
input on REFIN).
REFCOMP (Pin 12): Reference Buffer Output. REFCOMP
sets the full-scale input span. The reference buffer produces
an output voltage on the REFCOMP pin equal to 1.6384
times the voltage on the REFIN pin (4.096V on REFCOMP
for a 2.5V input on REFIN). REFIN tied to ground will
produce 2.048V on the REFCOMP pin. REFCOMP can be
driven externally if REFIN is tied to the positive supply.
Bypass to analog ground plane with 10μF tantalum in
parallel with 0.1μF ceramic or 10μF ceramic.
GND (Pins 13, 16): Ground. Tie to analog ground plane.
VDD (Pins 14, 15): Positive Supply. Bypass to analog
ground plane with 10μF tantalum in parallel with 0.1μF
ceramic or 10μF ceramic.
DIFFOUT/S6 (Pin 17): Three-State Digital Data Output.
Active when RD is low. Following a conversion, the
single-ended/differential bit of the present conversion is
available on this pin concurrent with the conversion result.
In Readback mode, the single-ended/differential bit of the
current sequencer location (S6) is available on this pin.
The output swings between OVDD and OGND.
A2OUT/S5, A1OUT/S4, A0OUT/S3 (Pins 18 to 20): Three-
State Digital MUX Address Outputs. Active when RD is low.
Following a conversion, the MUX address of the present
conversion is available on these pins concurrent with the
conversion result. In Readback mode, the MUX address of
the current sequencer location (S5-S3) is available on these
pins. The outputs swing between OVDD and OGND.
D9/S2 (Pin 21, LTC1852): Three-State Digital Data Output.
Active when RD is low. Following a conversion, bit 9 of the
present conversion is available on this pin. In Readback
mode, the unipolar/bipolar bit of the current sequencer
location (S2) is available on this pin. The output swings
between OVDD and OGND.
D11/S2 (Pin 21, LTC1853): Three-State Digital Data Output.
Active when RD is low. Following a conversion, bit 11 of
the present conversion is available on this pin. In Readback
mode, the unipolar/bipolar bit of the current sequencer
location (S2) is available on this pin. The output swings
between OVDD and OGND.
D8/S1 (Pin 22, LTC1852): Three-State Digital Data Outputs.
Active when RD is low. Following a conversion, bit 8 of the
present conversion is available on this pin. In Readback
mode, the gain bit of the current sequencer location (S1)
is available on this pin. The output swings between OVDD
and OGND.
D10/S1 (Pin 22, LTC1853): Three-State Digital Data
Outputs. Active when RD is low. Following a conversion,
bit 10 of the present conversion is available on this pin.
In Readback mode, the gain bit of the current sequencer
location (S1) is available on this pin. The output swings
between OVDD and OGND.
D7/S0 (Pin 23, LTC1852): Three-State Digital Data Outputs.
Active when RD is low. Following a conversion, bit 7 of the
present conversion is available on this pin. In Readback
mode, the end of sequence bit of the current sequencer
location (S0) is available on this pin. The output swings
between OVDD and OGND.
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