LTC1860C 데이터 시트보기 (PDF) - Linear Technology

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LTC1860C

µPower, 12-Bit, 250ksps 1- and 2-Channel ADCs in MSOP

Linear Technology 

LTC1860/LTC1861

FUNCTIONAL BLOCK DIAGRAM

PIN NAMES IN

PARENTHESES

REFER TO LTC1861

CONVERT

CLK

VCC

BIAS AND

SHUTDOWN

IN+

(CH0)

IN–

(CH1)

+

12-BIT

SAMPLING

–

ADC

CONV (SDI) SCK

SERIAL

SDO

PORT

DATA IN

12-BITS

DATA OUT

GND

VREF

1860/61 BD

TEST CIRCUITS

Load Circuit for tdDO, tr, tf, tdis and ten

TEST POINT

3k

SDO

20pF

VCC tdis WAVEFORM 2, ten

tdis WAVEFORM 1

1860 TC01

Voltage Waveforms for ten

CONV

SDO

1860 TC03

ten

Voltage Waveforms for SDO Delay Times, tdDO and thDO

SCK

VIL

tdDO

thDO

SDO

VOH

VOL

1860 TC02

Voltage Waveforms for SDO Rise and Fall Times, tr, tf

SDO

VOH

VOL

tr

tf

1860 TC04

Voltage Waveforms for tdis

CONV

VIH

SDO

WAVEFORM 1

(SEE NOTE 1)

90%

tdis

SDO

WAVEFORM 2

(SEE NOTE 2)

10%

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL

1860 TC05

18601fa

10

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