LTC1867LACGN 데이터 시트보기 (PDF) - Linear Technology
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LTC1867LACGN Datasheet PDF : 16 Pages
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LTC1863L/LTC1867L
TYPICAL CONNECTION DIAGRAM
±1.25V +
DIFFERENTIAL
INPUTS –
2.5V
SINGLE-ENDED
+
INPUT
CH0
VDD
CH1
GND
CH2
SDI
CH3
LTC1863L/
LTC1867L
SDO
CH4
SCK
CH5
CS/CONV
CH6
VREF
CH7/COM REFCOMP
2.7V TO 3.6V
10µF
DIGITAL
I/O
2.5V
10µF
1.25V
2.2µF
1863L7L TCD
TEST CIRCUITS
Load Circuits for Access Timing
2.7V
SDO
3k
CL
3k
SDO
CL
(A) Hi-Z TO VOH AND VOL TO VOH
(B) Hi-Z TO VOL AND VOH TO VOL
1863L7L TC01
Load Circuits for Output Float Delay
2.7V
3k
SDO
SDO
3k
CL
CL
(A) VOH TO Hi-Z
(B) VOL TO Hi-Z
1863L7L TC02
TIMING DIAGRAMS
t1 (For Short Pulse Mode)
t1
CS/CONV
50%
50%
1863L7L TD01a
CS/CONV
t4 (SDO Valid After CS/CONV↓)
t4
0.45V
t2 (SDO Valid After SCK↓)
t3 (SDO Valid Hold Time After SCK↓)
t2
SCK
0.45V
t3
SDO
1.9V
0.45V
1863L7L TD01b
t5 (SDI Setup Time Before SCK↑)
t6 (SDI Hold Time After SCK↑)
t5
t6
SCK
1.9V
8
SDO
SCK
CS/CONV
Hi-Z
1.9V
0.45V
1863L7L TD01c
t7 (SLEEP Mode Wake-Up Time)
t7
50%
SLEEP BIT (SLP = 0)
READ-IN
50%
1863L7L TD01e
SDI
CS/CONV
SDO
1.9V
0.45V
1.9V
0.45V
1863L7L TD01d
t8 (BUS Relinquish Time)
t8
1.9V
90%
10%
Hi-Z
1863L7L TD01f
1863l7lfd
For more information www.linear.com/LTC1863L
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