LTC2931HF 데이터 시트보기 (PDF) - Linear Technology

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LTC2931HF

Confi gurable Six Supply Monitor with Adjustable Reset and Watchdog Timers

Linear Technology 

LTC2931

APPLICATIONS INFORMATION

the negative voltage being sensed and the VREF pin, is

connected to the high impedance adjustable input (V4).

VREF provides the necessary level shift required to operate

at ground. The negative trip voltage is calculated from:

VTRIP

=

– VREF

•

R3

R4

;

VREF

=

1.210V

Nominal

In a negative adjustable application, the minimum value for

R4 is limited by the sourcing capability of VREF (±1mA).

With no other load on VREF, R4 (minimum) is:

1.210V

1mA

=

1.210kΩ

Tables 2 and 3 offer suggested 1% resistor values for

various positive and negative supply adjustable

applications assuming 5% monitor thresholds.

Although all six supply monitor comparators have built-

in glitch immunity, bypass capacitors on V1 and V2 are

recommended because the greater of V1 or V2 is also the

VCC for the device. Filter capacitors on the V3, V4, V5 and

V6 inputs are allowed.

Power-Down

On power-down, once any of the monitor inputs drops

below its threshold, RST is held at a logic low. A logic low

of 0.4V is guaranteed until both V1 and V2 drop below

1V. If the bandgap reference becomes invalid (VCC < 2V

typical), the LTC2931 will enter the 150μs setup period

when VCC rises above 2.4V max.

Watchdog Timer

The watchdog circuit monitors a microprocessor’s (μP)

activity. The μP is required to change the logic state of the

WDI pin on a periodic basis in order to clear the watchdog

timer. Whenever RST is low, the watchdog timer is cleared

and WDO is set high. The watchdog timer starts when RST

goes high. Subsequent edges received on the WDI pin

clear the watchdog timer. The watchdog timer continues

to run until it times out. Once it times out, internal circuitry

brings the WDO pin low. WDO remains low for one reset

timeout period unless it is cleared by another edge on the

WDI pin or RST goes low. WDO toggles between high and

low as long as the watchdog and reset timers are allowed

to time out repeatedly.

To disable the watchdog timer, simply ground the CWT

pin (Pin 11). With CWT held at ground, any reset event

forces WDO high indefinitely. It is safe to leave the WDI

pin unconnected because the weak internal pull-up (10μA

typical) pulls WDI high. Tying WDI to V1 or ground is also

allowed, but grounding the WDI pin forces the pull-up

current to be drawn continuously.

Selecting the Reset Timing Capacitor

The reset timeout period is adjustable in order to

accommodate a variety of microprocessor applications.

The reset timeout period, tRST, is adjusted by connecting

a capacitor, CRT, between the CRT pin and ground. The

value of this capacitor is determined by:

CRT

=

tRST

2MΩ

=

500⎡⎣pF

/

ms⎤⎦

•

tRST

Leaving the CRT pin unconnected generates a minimum

reset timeout of approximately 25μs. Maximum reset

timeout is limited by the largest available low leakage

capacitor. The accuracy of the timeout period is affected

by capacitor leakage (the nominal charging current is 2μA)

and capacitor tolerance. A low leakage ceramic capacitor

is recommended.

Selecting The Watchdog Timing Capacitor

The watchdog timeout period is adjustable and can be

optimized for software execution. The watchdog timeout

period, tWD, is adjusted by connecting a capacitor, CWT,

between the CWT pin and ground. The value of this

capacitor is determined by:

CWT

=

tWD

20MΩ

=

50⎡⎣pF

/

ms⎤⎦

•

tWD

Leaving the CWT pin unconnected generates a minimum

watchdog timeout of approximately 200μs. Maximum

watchdog timeout is limited by the largest available low

leakage capacitor. The accuracy of the timeout period is

affected by capacitor leakage (the nominal charging current

is 2μA) and capacitor tolerance. A low leakage ceramic

capacitor is recommended.

2931fb

11

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