LTC3418 데이터 시트보기 (PDF) - Linear Technology

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LTC3418

8A, 4MHz, Monolithic Synchronous Step-Down Regulator

Linear Technology 

LTC3418

OPERATION

Main Control Loop

The LTC3418 is a monolithic, constant frequency, current

mode step-down DC/DC converter. During normal opera-

tion, the internal top power switch (P-channel MOSFET) is

turned on at the beginning of each clock cycle. Current in

the inductor increases until the current comparator trips

and turns off the top power MOSFET. The peak inductor

current at which the current comparator shuts off the top

power switch is controlled by the voltage on the ITH pin.

The error amplifier adjusts the voltage on the ITH pin by

comparing the feedback signal from a resistor divider on

the VFB pin with an internal 0.8V reference. When the load

current increases, it causes a reduction in the feedback

voltage relative to the reference. The error amplifier raises

the ITH voltage until the average inductor current matches

the new load current. When the top power MOSFET shuts

off, the synchronous power switch (N-channel MOSFET)

turns on until either the bottom current limit is reached or

the beginning of the next clock cycle. The bottom current

limit is set at –8A for force continuous mode and 0A for

Burst Mode operation.

The operating frequency is externally set by an external

resistor connected between the RT pin and ground. The

practical switching frequency can range from 300kHz to

4MHz.

Overvoltage and undervoltage comparators will pull the

PGOOD output low if the output voltage comes out of

regulation by ±7.5%. In an overvoltage condition, the top

power MOSFET is turned off and the bottom power MOSFET

is switched on until either the overvoltage condition clears

or the bottom MOSFET’s current limit is reached.

Forced Continuous

Connecting the SYNC/MODE pin to SVIN will disable Burst

Mode operation and force continuous current operation.

At light loads, forced continuous mode operation is less

efficient than Burst Mode operation, but may be desirable

in some applications where it is necessary to keep switch-

ing harmonics out of a signal band. The output voltage

ripple is minimized in this mode.

Burst Mode Operation

Connecting the SYNC/MODE pin to a voltage in the range

of 0V to 1V enables Burst Mode operation. In Burst Mode

operation, the internal power MOSFETs operate intermit-

tently at light loads. This increases efficiency by minimiz-

ing switching losses. During Burst Mode operation, the

minimum peak inductor current is externally set by the

voltage on the SYNC/MODE pin and the voltage on the ITH

pin is monitored by the burst comparator to determine

when sleep mode is enabled and disabled. When the

average inductor current is greater than the load current,

the voltage on the ITH pin drops. As the ITH voltage falls

below 350mV, the burst comparator trips and enables

sleep mode. During sleep mode, the top power MOSFET

is held off while the load current is solely supplied by the

output capacitor. When the output voltage drops, the top

and bottom power MOSFETs begin switching to bring the

output back into regulation. This process repeats at a rate

that is dependent on the load demand.

Pulse skipping operation can be implemented by connect-

ing the SYNC/MODE pin to ground. This forces the burst

clamp level to be at 0V. As the load current decreases, the

peak inductor current will be determined by the voltage

on the ITH pin until the ITH voltage drops below 400mV. At

this point, the peak inductor current is determined by the

minimum on-time of the current comparator. If the load

demand is less than the average of the minimum on-time

inductor current, switching cycles will be skipped to keep

the output voltage in regulation.

Frequency Synchronization

The internal oscillator of the LTC3418 can by synchronized

to an external clock connected to the SYNC/MODE pin.

The frequency of the external clock can be in the range

of 300kHz to 4MHz.

For this application, the oscillator timing resistor should

be chosen to correspond to a frequency that is 25% lower

than the synchronization frequency. During synchroniza-

tion, the burst clamp is set to 0V, and each switching cycle

begins at the falling edge of the clock signal.

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