M24164-BN3 데이터 시트보기 (PDF) - STMicroelectronics

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M24164-BN3

16 Kbit Serial I2C BUS EEPROM

STMicroelectronics 

M24164

Figure 6. I2C Bus Protocol

SCL

SDA

START

CONDITION

SDA

SDA

INPUT CHANGE

STOP

CONDITION

SCL

SDA

1

2

3

MSB

START

CONDITION

SCL

SDA

1

2

3

MSB

7

8

9

ACK

7

8

9

ACK

STOP

CONDITION

AI00792

Minimizing System Delays by Polling On ACK.

During the internal write cycle, the memory discon-

nects itself from the bus in order to copy the data

from the internal latches to the memory cells. The

maximum value of the write time (tW) is given in the

AC Characteristics table, since the typical time is

shorter, the time seen by the system may be re-

duced by an ACK polling sequence issued by the

master. The sequence is:

– Initial condition: a Write is in progress (see Figure

7).

– Step 1: the master issues a START condition

followed by a Device Select byte (1st byte of the

new instruction).

– Step 2: if the memory is busy with the internal

write cycle, NoACK will be returned and the

master goes back to Step 1. If the memory has

terminated the internal write cycle, it will respond

with an ACK, indicating that the memory is ready

to receive the second part of the incoming in-

struction (the first byte of this instruction was

already sent during Step 1).

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