M25P05-AVMB6G 데이터 시트보기 (PDF) - Numonyx -> Micron

부품명

상세내역

제조사

M25P05-AVMB6G

512-Kbit, serial flash memory, 50 MHz SPI bus interface

Numonyx -> Micron 

Instructions

M25P05-A

6.4

Read status register (RDSR)

The read status register (RDSR) instruction allows the status register to be read. The status

register may be read at any time, even while a program, erase or write status register cycle

is in progress. When one of these cycles is in progress, it is recommended to check the

write in progress (WIP) bit before sending a new instruction to the device. It is also possible

to read the status register continuously, as shown in Figure 10.

Table 6. Status register format

b7

SRWD

0

0

0

b0

BP1

BP0

WEL

WIP

6.4.1

6.4.2

6.4.3

6.4.4

Status register write protect

Block protect bits

Write enable latch bit

Write in progress bit

The status and control bits of the status register are as follows:

WIP bit

The write in progress (WIP) bit indicates whether the memory is busy with a write status

register, program or erase cycle. When set to ‘1’, such a cycle is in progress, when reset to

‘0’ no such cycle is in progress.

WEL bit

The write enable latch (WEL) bit indicates the status of the internal write enable latch. When

set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is

reset and no write status register, program or erase instruction is accepted.

BP1, BP0 bits

The block protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against program and erase instructions. These bits are written with the

write status register (WRSR) instruction. When one or both of the block protect (BP1, BP0)

bits is set to ‘1’, the relevant memory area (as defined in Table 2) becomes protected

against page program (PP) and sector erase (SE) instructions. The block protect (BP1,

BP0) bits can be written provided that the hardware protected mode has not been set. The

bulk erase (BE) instruction is executed if, and only if, both block protect (BP1, BP0) bits are

0.

SRWD bit

The status register write disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. The status register write disable (SRWD) bit and write protect (W) signal

allow the device to be put in the hardware protected mode (when the status register write

disable (SRWD) bit is set to ‘1’, and write protect (W) is driven Low). In this mode, the non-

volatile bits of the status register (SRWD, BP1, BP0) become read-only bits and the write

status register (WRSR) instruction is no longer accepted for execution.

22/52

Share Link: