M25P05-AVMB6G 데이터 시트보기 (PDF) - Numonyx -> Micron

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M25P05-AVMB6G

512-Kbit, serial flash memory, 50 MHz SPI bus interface

Numonyx -> Micron 

Instructions

M25P05-A

6.9

Sector erase (SE)

The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it

can be accepted, a write enable (WREN) instruction must previously have been executed.

After the write enable (WREN) instruction has been decoded, the device sets the write

enable latch (WEL).

The sector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, and three address bytes on Serial Data input (D). Any address inside the

sector (see Table 3) is a valid address for the sector erase (SE) instruction. Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

Chip Select (S) must be driven High after the eighth bit of the last address byte has been

latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip

Select (S) is driven High, the self-timed sector erase cycle (whose duration is tSE) is

initiated. While the sector erase cycle is in progress, the status register may be read to

check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during

the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time

before the cycle is completed, the write enable latch (WEL) bit is reset.

A sector erase (SE) instruction applied to a page which is protected by the block protect

(BP1, BP0) bits (see Table 3 and Table 2) is not executed.

Figure 15. Sector erase (SE) instruction sequence

S

0123456789

29 30 31

C

Instruction

24-bit address

D

23 22

210

MSB

1. Address bits A23 to A16 must be set to 00h.

AI03751D

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