M27C160-90S1 데이터 시트보기 (PDF) - STMicroelectronics
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M27C160-90S1 Datasheet PDF : 19 Pages
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M27C160
Figure 10. Programming and Verify Modes AC Waveforms
A0-A19
Q0-Q15
BYTEVPP
VCC
E
G
tAVEL
DATA IN
tQVEL
VALID
tEHQX
DATA OUT
tVPHAV
tGLQV
tVCHAV
tELEH
tQXGL
PROGRAM
VERIFY
tGHQZ
tGHAX
AI00744
Figure 11. Programming Flowchart
VCC = 6.25V, VPP = 12.5V
n=0
NO
++n
= 25
YES
E = 50µs Pulse
NO
VERIFY
YES
++ Addr
FAIL
Last NO
Addr
YES
CHECK ALL WORDS
BYTEVPP =VIH
1st: VCC = 6V
2nd: VCC = 4.2V
AI01044B
10/19
PRESTO III Programming Algorithm
The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaran-
teed margin in a typical time of 52.5 seconds. Pro-
gramming with PRESTO III consists of applying a
sequence of 50µs program pulses to each word
until a correct verify occurs (see Figure 11). During
programing and verify operation a MARGIN
MODE circuit is automatically activated to guaran-
tee that each cell is programed with enough mar-
gin. No overprogram pulse is applied since the
verify in MARGIN MODE provides the necessary
margin to each programmed cell.
Program Inhibit
Programming of multiple M27C160s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C160 may be common. A TTL low level pulse
applied to a M27C160's E input and VPP at 12.5V,
will program that M27C160. A high level E input in-
hibits the other M27C160s from being pro-
grammed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
at VIH and G at VIL, VPP at 12.5V and VCC at
6.25V.
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