X28LC512 데이터 시트보기 (PDF) - Xicor -> Intersil

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X28LC512

3.3 Volt, Byte Alterable E2PROM

Xicor -> Intersil 

X28LC512/X28LC513

The Toggle Bit I/O6

Figure 3a. Toggle Bit Bus Sequence

LAST

WE WRITE

CE

OE

I/O6

VOH

*

VOL

* Beginning and ending state of I/O6 will vary.

Figure 3b. Toggle Bit Software Flow

LAST WRITE

LOAD ACCUM

FROM ADDR n

COMPARE

ACCUM WITH

ADDR n

HIGH Z

*

X28LC512

READY

3005 ILL F14

The Toggle Bit can eliminate the software housekeeping

chore of saving and fetching the last address and data

written to a device in order to implement DATA Polling.

This can be especially helpful in an array comprised of

multiple X28LC512/513 memories that is frequently

updated. Toggle Bit Polling can also provide a method

for status checking in multiprocessor applications. The

timing diagram in Figure 3a illustrates the sequence of

events on the bus. The software flow diagram in Figure

3b illustrates a method for polling the Toggle Bit.

COMPARE

NO

OK?

YES

X28LC512

READY

3005 ILL F15

5

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