X28HT512 데이터 시트보기 (PDF) - Xicor -> Intersil

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X28HT512

High Temperature, 5 Volt, Byte Alterable E2PROM

Xicor -> Intersil 

X28HT512

CE Controlled Write Cycle

ADDRESS

CE

OE

WE

DATA IN

tAS

tOES

tCS

tDV

DATA OUT

tAH

tCW

tWC

tWPH

tOEH

tCH

DATA VALID

tDS

tDH

HIGH Z

6614 FHD F07

Page Write Cycle

OE (5)

CE

WE

ADDRESS * (6)

tWP

tBLC

tWPH

I/O

BYTE 0

BYTE 1

BYTE 2

BYTE n

BYTE n+1

*For each successive write within the page write operation, A7–A15 should be the same or

writes to an unknown address could occur.

LAST BYTE

BYTE n+2

tWC

6614 FHD F08

Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH

to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing

a polling operation.

(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform

to either the CE or WE controlled write cycle timing.

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