IS61NLF51218-10BI 데이터 시트보기 (PDF) - Integrated Silicon Solution
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IS61NLF51218-10BI
Integrated Silicon Solution
IS61NLF51218-10BI Datasheet PDF : 20 Pages
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IS61NF25632 IS61NF25636 IS61NF51218
IS61NLF25632 IS61NLF25636 IS61NLF51218
STATE DIAGRAM
ISSI ®
READ
BEGIN
READ
DS
READ
READ
WRITE
DS
WRITE
BEGIN
WRITE
WRITE
READ BURST
BURST
BURST
READ
DESELECT
BURST WRITE
DS
BURST
DS
WRITE
DS
READ
BURST
WRITE
BURST
SYNCHRONOUS TRUTH TABLE(1)
Operation
Address
Used
CS1 CS2 CS2 ADV WE BWx OE CKE CLK
Not Selected Continue
N/A
X
X
X
H
X
X
X
L
↑
Begin Burst Read
External Address L
H
L
L
H
X
L
L
↑
Continue Burst Read
Next Address
X
X
X
H
X
X
L
L
↑
NOP/Dummy Read
External Address L
H
L
L
H
X
H
L
↑
Dummy Read
Next Address
X
X
X
H
X
X
H
L
↑
Begin Burst Write
External Address L
H
L
L
L
L
X
L
↑
Continue Burst Write
Next Address
X
X
X
H
X
L
X
L
↑
NOP/Write Abort
N/A
L
H
L
L
L
H
X
L
↑
Write Abort
Next Address
X
X
X
H
X
H
X
L
↑
Ignore Clock
Current Address X
X
X
X
X
X
X
H
↑
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
04/26/01
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