MT55L256V32PB-7.5IT 데이터 시트보기 (PDF) - Micron Technology
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MT55L256V32PB-7.5IT Datasheet PDF : 30 Pages
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8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
TQFP PIN DESCRIPTIONS
x18
37
36
32-35, 44-50,
80-83, 99, 100
93
94
–
–
89
98
92
97
86
85
87
64
x32/x36
37
36
32-35, 44-50,
81-83, 99, 100
93
94
95
96
89
98
92
97
86
85
87
64
SYMBOL TYPE
SA0 Input
SA1
SA
BWa#
BWb#
BWc#
BWd#
Input
CLK Input
CE# Input
CE2# Input
CE2 Input
OE# Input
(G#)
ADV/LD# Input
CKE# Input
ZZ Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered
and must meet the setup and hold times around the rising
edge of CLK. Pin 84 is reserved as an address bit for
higher-density 18Mb ZBT SRAMs. SA0 and SA1 are the
two least significant bits (LSB) of the address field and
set the internal burst counter if burst is desired.
Synchronous Byte Write Enables: These active LOW inputs
allow individual bytes to be written when a WRITE cycle is
active and must meet the setup and hold times around the
rising edge of CLK. BYTE WRITEs need to be asserted on
the same cycle as the address. BWs are associated with
addresses and apply to subsequent data. BWa# controls
DQa pins; BWb# controls DQb pins; BWc# controls DQc
pins; BWd# controls DQd pins.
Clock: This signal registers the address, data, chip enables,
byte write enables, and burst control inputs on its rising
edge. All synchronous inputs must meet setup and hold
times around the clock’s rising edge.
Synchronous Chip Enable: This active LOW input is used to
enable the device and is sampled only when a new
external address is loaded (ADV/LD# is LOW).
Synchronous Chip Enable: This active LOW input is used to
enable the device and is sampled only when a new
external address is loaded (ADV/LD# is LOW). This
input can be used for memory depth expansion.
Synchronous Chip Enable: This active HIGH input is used to
enable the device and is sampled only when a new
external address is loaded (ADV/LD# is LOW). This
input can be used for memory depth expansion.
Output Enable: This active LOW, asynchronous input
enables the data I/O output drivers. G# is the JEDEC-
standard term for OE#.
Synchronous Address Advance/Load: When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is
loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW
on ADV/LD# clocks a new address at the CLK rising edge.
Synchronous Clock Enable: This active LOW input permits
CLK to propagate throughout the device. When CKE# is
HIGH, the device ignores the CLK input and effectively
internally extends the previous CLK cycle. This input must
meet setup and hold times around the rising edge of CLK.
Snooze Enable: This active HIGH, asynchronous input
causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When ZZ is
active, all other inputs are ignored.
(continued on next page)
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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