IS61VPD51236-166TQ 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS61VPD51236-166TQ

512K x 32, 512K x 36, 1024K x 18 SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

Integrated Silicon Solution 

ISSI ®

IS61VPD51232 IS61VPD51236 IS61VPD10018

512K x 32, 512K x 36, 1024K x 18

SYNCHRONOUS PIPELINED,

DOUBLE CYCLE DESELECT STATIC RAM

ADVANCE INFORMATION

SEPTEMBER 2001

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Linear burst sequence control using MODE input

• Three chip enable option for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and

119-pin PBGA package

• Single +2.5V, ±5% operation

• Auto Power-down during deselect

• Double cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

FAST ACCESS TIME

Symbol

tKQ

tKC

Parameter

Clock Access Time

Cycle Time

Frequency

DESCRIPTION

The ISSI IS61VPD51232, IS61VPD51236, and

IS61VPD10018 are high-speed, low-power synchronous

static RAMs designed to provide burstable, high-performance

memory for communication and networking applications.

The IS61VPD51232 is organized as 524,288 words by 32 bits

and the IS61VPD51236 is organized as 524,288 words by

36 bits. The IS61VPD10018 is organized as 1,048,576

words by 18 bits. Fabricated with ISSI's advanced CMOS

technology, the device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit. All synchronous inputs

pass through registers controlled by a positive-edge-

triggered single clock input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

Byte write operation is performed by using byte write

enable (BWE).input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the ADV (burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

-200

-166

Units

3.1

3.5

ns

5

6

ns

200

166

MHz

This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best

possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

ADVANCE INFORMATION Rev. 00B

09/25/01

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