IS61VPD51236-200TQI 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS61VPD51236-200TQI

512K x 32, 512K x 36, 1024K x 18 SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

Integrated Silicon Solution 

IS61VPD51232 IS61VPD51236 IS61VPD10018

ISSI ®

PIN CONFIGURATION

119-pin PBGA (Top View)

1

2

3

4

5

6

7

A

VCCQ

A

A

ADSP

A

A

VCCQ

B

NC

A

A

ADSC

A

A

NC

C

NC

A

A

VCC

A

A

NC

D

DQc DQPc GND

NC

GND DQPb DQb

E

DQc

DQc GND

CE

GND DQb

DQb

F

VCCQ DQc GND

OE

GND DQb VCCQ

G

DQc

DQc

BWc ADV BWb DQb

DQb

H

DQc

DQc GND

GW

GND DQb

DQb

J

VCCQ VCC

NC

VCC

NC

VCC VCCQ

K

DQd DQd GND CLK GND DQa DQa

L

DQd

DQd BWd

NC

BWa DQa DQa

M

VCCQ

DQd

GND BWE GND

DQa VCCQ

N

DQd

DQd GND

A1

GND DQa DQa

P

DQd DQPd GND

A0

GND DQPa DQa

R

NC

A

MODE VCC

NC

A

NC

T

NC

NC

A

A

A

NC

ZZ

U

VCCQ TMS

TDI

TCK TDO

NC VCCQ

100-Pin TQFP

DQPc

DQc

DQc

VCCQ

GND

DQc

DQc

DQc

DQc

GND

VCCQ

DQc

DQc

NC

VCC

NC

GND

DQd

DQd

VCCQ

GND

DQd

DQd

DQd

DQd

GND

VCCQ

DQd

DQd

DQPd

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

2

79

3

78

4

77

5

76

6

75

7

74

8

73

9

72

10

71

11

70

12

69

13

68

14

67

15

66

16

65

17

64

18

63

19

62

20

61

21

60

22

59

23

58

24

57

25

56

26

55

27

54

28

53

29

52

30

51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

DQPb

DQb

DQb

VCCQ

GND

DQb

DQb

DQb

DQb

GND

VCCQ

DQb

DQb

GND

NC

VCC

ZZ

DQa

DQa

VCCQ

GND

DQa

DQa

DQa

DQa

GND

VCCQ

DQa

DQa

DQPa

512K x 36

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These

pins must tied to the two LSBs of the

address bus.

A

ADSC

ADSP

Synchronous Address Inputs

Synchronous Controller Address Status

Synchronous Processor Address Status

ADV

BWa-BWd

BWE

Synchronous Burst Address Advance

Synchronous Byte Write Enable

Synchronous Byte Write Enable

CE, CE2, CE2 Synchronous Chip Enable

CLK

Synchronous Clock

DQa-DQd

Synchronous Data Input/Output

DQPa-DQPd

GND

GW

MODE

OE

TMS, TDI,

TCK, TDO

VCC

VCCQ

ZZ

Parity Data Input/Output

Ground

Synchronous Global Write Enable

Burst Sequence Mode Selection

Output Enable

JTAG Boundary Scan Pins

+2.5V Power Supply

Isolated Output Buffer Supply:

+2.5V

Snooze Enable

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION Rev. 00B

09/25/01

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