IS61VPD10018-166TQ 데이터 시트보기 (PDF) - Integrated Silicon Solution
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IS61VPD10018-166TQ
Integrated Silicon Solution
IS61VPD10018-166TQ Datasheet PDF : 24 Pages
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IS61VPD51232 IS61VPD51236 IS61VPD10018
ISSI ®
TRUTH TABLE(1-8) (1CE option)
NEXT CYCLE
ADDRESS CE ADSP ADSC ADV WRITE OE
DQ
Deselected
None H
X
L
X
X
X
High-Z
Read, Begin
External L
L
X
X
X
L
Q
Read, Begin
External L
L
X
X
X
H
High-Z
Write, Begin
External L
H
L
X
Write
X
D
Read, Begin
External L
H
L
X
Read
L
Q
Read, Begin
External L
H
L
X Read H
High-Z
Read, Burst
Next
X
H
H
L
Read
L
Q
Read, Burst
Next
X
H
H
L
Read
H
High-Z
Read, Burst
Next
H
X
H
L
Read
L
Q
Read, Burst
Next
H
X
H
L
Read
H
High-Z
Write, Burst
Next
X
H
H
L
Write
X
D
Write, Burst
Next
H
X
H
L
Write
X
D
Read, Suspend
Current X
H
H
H
Read
L
Q
Read, Suspend
Current X
H
H
H Read H
High-Z
Read, Suspend
Current H
X
H
H
Read
L
Q
Read, Suspend
Current H
X
H
H Read H
High-Z
Write, Suspend
Current X
H
H
H Write X
D
Write, Suspend
Current H
X
H
H Write X
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW.
WRITE = H for all BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and
DQPd are only available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the
input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE
Function
GW BWE
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
H
H
H
L
H
L
H
L
L
X
BWa
X
H
L
L
X
BWb
X
H
H
L
X
BWc
X
H
H
L
X
BWd
X
H
H
L
X
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
ADVANCE INFORMATION Rev. 00B
09/25/01
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