M28C64 데이터 시트보기 (PDF) - STMicroelectronics
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M28C64 Datasheet PDF : 24 Pages
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M28C64
Table 3. Operating Modes 1
Mode
E
G
W
Stand-by
1
X
X
Output Disable
X
1
X
Write Disable
X
X
1
Read
0
0
1
Write
0
1
0
Chip Erase
0
V
0
Note: 1. 0=VIL; 1=VIH; X = VIH or VIL; V=12V ± 5%.
DQ0-DQ7
Hi-Z
Hi-Z
Hi-Z
Data Out
Data In
Hi-Z
SIGNAL DESCRIPTION
The external connections to the device are
summarized in Table 1, and their use in Table 3.
Addresses (A0-A12). The address inputs are
used to select one byte from the memory array
during a read or write operation.
Data In/Out (DQ0-DQ7). The contents of the data
byte are written to, or read from, the memory array
through the Data I/O pins.
Chip Enable (E). The chip enable input must be
held low to enable read and write operations.
When Chip Enable is high, power consumption is
reduced.
Output Enable (G). The Output Enable input
controls the data output buffers, and is used to
initiate read operations.
Write Enable (W). The Write Enable input controls
whether the addressed location is to be read, from
or written to.
Ready/Busy (RB). Ready/Busy is an open drain
output that can be used to detect the end of the
internal write cycle.
DEVICE OPERATION
In order to prevent data corruption and inadvertent
write operations, an internal VCC comparator
inhibits the Write operations if the VCC voltage is
lower than VWI (see Table 4A and Table 4B). Once
the voltage applied on the VCC pin goes over the
VWI threshold (VCC>VWI), write access to the
memory is allowed after a time-out tPUW, as
specified in Table 4A and Table 4B.
Further protection against data corruption is
offered by the E and W low pass filters: any glitch,
on the E and W inputs, with a pulse width less than
10 ns (typical) is internally filtered out to prevent
inadvertent write operations to the memory.
Table 4A. Power-Up Timing1 for M28C64 (5V range)
(TA = 0 to 70 °C or –40 to 85 °C or –40 to 125 °C; VCC = 4.5 to 5.5 V)
Symbol
Parameter
Min.
Max.
Unit
tPUR
Time Delay to Read Operation
1
µs
tPUW
Time Delay to Write Operation (once VCC ≥ VWI)
10
ms
VWI
Write Inhibit Threshold
Note: 1. Sampled only, not 100% tested.
3.0
4.2
V
Table 4B. Power-Up Timing1 for M28C64-xxW (3V range)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol
Parameter
tPUR
Time Delay to Read Operation
tPUW
Time Delay to Write Operation (once VCC ≥ VWI)
VWI
Write Inhibit Threshold
Note: 1. Sampled only, not 100% tested.
Min.
Max.
Unit
1
µs
15
ms
1.5
2.5
V
4/24
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