MT28F004B5WG-8T(Rev3) 데이터 시트보기 (PDF) - Micron Technology
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MT28F004B5WG-8T Datasheet PDF : 32 Pages
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4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
Memory Array
A WRITE to the memory array sets the desired bits
to logic 0s but cannot change a given bit to a logic 1
from a logic 0. Setting any bits to a logic 1 requires that
the entire block be erased. To perform a WRITE, OE#
must be HIGH, CE# and WE# must be LOW, and VPP
must be set to VPPH. Writing to the boot block also
requires that the RP# pin be at VHH or WP# be HIGH.
A0–A17/(A18) provide the address to be written, while
the data to be written to the array is input on the DQ
pins. The data and addresses are latched on the rising
edge of CE# (CE#-controlled) or WE# (WE#-con-
trolled), whichever occurs first. A WRITE must be pre-
ceded by a WRITE SETUP command. Details on how to
input data to the array are described in the Write
Sequence section.
Selectable bus sizing applies to WRITEs as it does to
READs on the MT28F400B5. When BYTE# is LOW (byte
mode), data is input on DQ0–DQ7, DQ8–DQ14 are
High-Z and DQ15 becomes the lowest order address
input. When BYTE# is HIGH (word mode), data is
input on DQ0–DQ15.
COMMAND SET
To simplify writing of the memory blocks, the
MT28F004B5 and MT28F400B5 incorporate an ISM
that controls all internal algorithms for the WRITE and
ERASE cycles. An 8-bit command set is used to control
the device. Details on how to sequence commands are
provided in the Command Execution section. Table 1
lists the valid commands.
Table 1: Command Set
COMMAND
RESERVED
READ ARRAY
IDENTIFY DEVICE
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP
ERASE CONFIRM/RESUME
WRITE SETUP
ERASE SUSPEND
HEX CODE
00h
FFh
90h
70h
50h
20h
D0h
40h or 10h
B0h
DESCRIPTION
This command and all unlisted commands are invalid and should not be
called. These commands are reserved to allow for future feature
enhancements.
Must be issued after any other command cycle before the array can be read.
It is not necessary to issue this command after power-up or RESET.
Allows the device ID and manufacturer compatibility ID to be read. A0 is
used to decode between the manufacturer compatibility ID (A0 = LOW) and
device ID (A0 = HIGH).
Allows the status register to be read. Please refer to Table 2 for more
information on the status register bits.
Clears status register bits 3–5, which cannot be cleared by the ISM.
The first command given in the two-cycle ERASE sequence. The ERASE is not
completed unless followed by ERASE CONFIRM.
The second command given in the two-cycle ERASE sequence. Must follow
an ERASE SETUP command to be valid. Also used during an ERASE SUSPEND
to resume the ERASE.
The first command given in the two-cycle WRITE sequence. The write data
and address are given in the following cycle to complete the WRITE.
Requests a halt of the ERASE and puts the device into the erase suspend
mode. When the device is in this mode, only READ STATUS REGISTER, READ
ARRAY and ERASE RESUME commands may be executed.
4Mb Smart 5 Boot Block Flash Memory
MT28F004B5_3.fm - Rev. 3, Pub. 8/2002
11
©2002, Micron Technology Inc.
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