MT28F400B5WG-8TET(Rev3) 데이터 시트보기 (PDF) - Micron Technology
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MT28F400B5WG-8TET Datasheet PDF : 32 Pages
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4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
PIN DESCRIPTIONS
44-PIN SOP
NUMBERS
43
40-PIN
TSOP
NUMBERS
9
48-PIN
TSOP
NUMBERS
11
SYMBOL
WE#
2
12
14
WP#
12
22
26
CE#
44
10
12
RP#
14
24
28
OE#
33
–
47
BYTE#
11, 10, 9, 8, 21, 20, 19,
7, 6, 5, 4,
18, 17,
42, 41, 40, 16,15, 14, 8,
39, 38, 37, 7, 36, 6, 5,
36, 35, 34, 3 4, 3, 2, 1,
40, 13
31
–
25, 24, 23,
22, 21, 20,
19, 18, 8, 7,
6, 5, 4, 3, 2,
1, 48, 17
45
A0–A17/
(A18)
DQ15
(A-1)
15, 17, 19,
21, 24, 26,
28, 30
16, 18, 20,
22, 25, 27,
29
1
25-28, 32-35
–
11
29, 31, 33,
35, 38, 40,
42, 44
30, 32, 34,
36, 39, 41,
43
13
DQ0–DQ7
DQ8–
DQ14
VPP
23
13, 32
–
30, 31
37
VCC
23, 39
27, 46
VSS
29, 37, 38 9, 10, 15, 16
NC
TYPE
Input
Input
Input
Input
Input
Input
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a WRITE cycle.
If WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
Write Protect: Unlocks the boot block when HIGH if VPP =
5V and RP# = VIH during a WRITE or ERASE. Does not affect
WRITE or ERASE operation on other blocks.
Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
Reset/Power-Down: When LOW, RP# clears the status
register, sets the internal state machine (ISM) to the array
read mode and places the device in deep power-down
mode. All inputs, including CE#, are “Don’t Care,” and all
outputs are High-Z. RP# unlocks the boot block and
overrides the condition of WP# when at VHH, and must be
held at VIH during all other modes of operation.
Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
Byte Enable: If BYTE# = HIGH, the upper byte is active
through DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are
High-Z, and all data is accessed through DQ0–DQ7. DQ15/
(A-1) becomes the least significant address input.
Address Inputs: Select a unique, 16-bit word or 8-bit byte.
The Q15/(A-1) input becomes the lowest order address
when BYTE# = LOW (MT28F400B5) to allow for a selection
of an 8-bit byte from the 524,288 available.
Input/
Output
Input/
Output
Input/
Output
Supply
Supply
Supply
–
Data I/O: MSB of data when BYTE# = HIGH. Address Input:
LSB of address input when BYTE# = LOW during READ or
WRITE operation.
Data I/Os: Data output pins during any READ operation or
data input pins during a WRITE. These pins are used to
input commands to the CEL.
Data I/Os: Data output pins during any READ operation or
data input pins during a WRITE when BYTE# = HIGH. These
pins are High-Z when BYTE# is LOW.
Write/Erase Supply Voltage: From a WRITE or ERASE
CONFIRM until completion of the WRITE or ERASE, VPP
must be at VPPH (5V). VPP = “Don’t Care” during all other
operations.
Power Supply: +5V ±10%.
Ground.
No Connect: These pins may be driven or left unconnected.
4Mb Smart 5 Boot Block Flash Memory
MT28F004B5_3.fm - Rev. 3, Pub. 8/2002
4
©2002, Micron Technology Inc.
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