MT28F004B5WG-8T(Rev3) 데이터 시트보기 (PDF) - Micron Technology

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MT28F004B5WG-8T
(Rev.:Rev3)

FLASH MEMORY

Micron Technology 

4Mb

SMART 5 BOOT BLOCK FLASH MEMORY

tional error information is set in three other bits: VPP

status, write status, and erase status.

Command Execution Logic (CEL)

The CEL receives and interprets commands to the

device. These commands control the operation of the

ISM and the read path (i.e., memory array, ID register

or status register). Commands may be issued to the

CEL while the ISM is active. However, there are restric-

tions on what commands are allowed in this condition.

See the Command Execution section for more detail.

Deep Power-down Mode

To allow for maximum power conservation, the

MT28F004B5 and MT28F400B5 feature a very low cur-

rent, deep power-down mode. To enter this mode, the

RP# pin is taken to VSS ±0.2V. In this mode, the current

draw is a maximum of 20µA at 5V VCC. Entering deep

power-down also clears the status register and sets the

ISM to the read array mode.

MEMORY ARCHITECTURE

The MT28F004B5 and MT28F400B5 memory array

architecture is designed to allow sections to be erased

without disturbing the rest of the array. The array is

divided into seven addressable blocks that vary in size

and are independently erasable. When blocks rather

than the entire array are erased, total device endur-

ance is enhanced, as is system flexibility. Only the

ERASE function is block-oriented. All READ and

WRITE operations are done on a random-access basis.

The boot block is protected from unintentional

ERASE or WRITE operations with a hardware protec-

tion circuit that requires a super-voltage be applied to

RP# or that the WP# pin be driven HIGH before erasure

is commenced. The boot block is intended for the core

firmware required for basic system functionality. The

remaining six blocks do not require that either of these

two conditions be met before WRITE or ERASE opera-

tions.

Boot Block

The hardware-protected boot block provides extra

security for the most sensitive portions of the firm-

ware. This 16KB block may only be erased or written

when the RP# pin is at the specified boot block unlock

voltage (VHH) or when the WP# pin is VIH. During a

WRITE or ERASE of the boot block, the RP# pin must

be held at VHH or the WP# pin held HIGH until the

ERASE or WRITE is completed. The VPP pin must be at

VPPH (5V) when the boot block is written to or erased.

The MT28F004B5 and MT28F400B5 are available in

two configurations and top or bottom boot block. The

top boot block version supports processors of the x86

variety. The bottom boot block version is intended for

680X0 and RISC applications. Figure 1 illustrates the

memory address maps associated with these two ver-

sions.

Parameter Blocks

The two 8KB parameter blocks store less sensitive

and more frequently changing system parameters and

also may store configuration or diagnostic coding.

These blocks are enabled for erasure when the VPP pin

is at VPPH. No super-voltage unlock or WP# control is

required.

Main Memory Blocks

The four remaining blocks are general-purpose

memory blocks and do not require a super-voltage on

RP# or WP# control to be erased or written. These

blocks are intended for code storage, ROM-resident

applications or operating systems that require in-sys-

tem update capability.

4Mb Smart 5 Boot Block Flash Memory

MT28F004B5_3.fm - Rev. 3, Pub. 8/2002

8

©2002, Micron Technology Inc.

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