IS42S32200A-6T 데이터 시트보기 (PDF) - Integrated Silicon Solution
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IS42S32200A-6T
Integrated Silicon Solution
IS42S32200A-6T Datasheet PDF : 55 Pages
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IS42S32200A
ISSI ®
PIN FUNCTIONS
Symbol
A0-A10
Pin No.
25 to 27
60 to 66
24
Type
Input Pin
BA0, BA1
22,23
CAS
18
CKE
67
Input Pin
Input Pin
Input Pin
CLK
68
Input Pin
CS
20
Input Pin
I/O0 to
I/O31
2, 4, 5, 7, 8, 10,11,13
74,76,77,79,80,82,83,85
45,47,48,50,51,53,54,56
31,33,34,36,37,39,40,42
DQM0
DQM3
16,28,59,71
I/O Pin
Input Pin
RAS
19
Input Pin
WE
17
Input Pin
VCCQ
VCC
GNDQ
GND
3,9,35,41,49,55,25,81
1,15,29,43
6,12,32,38,46,52,78,84
44,58,72,86
Supply Pin
Supply Pin
Supply Pin
Supply Pin
Function (In Detail)
Address Inputs: A0-A10 are sampled during the ACTIVE
command (row-address A0-A10) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down mode, clock suspend mode,
or self refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units
using the DQM0-DQM3 pins
DQMx control thel ower and upper bytes of the I/O buffers. In read mode,
the output buffers are place in a High-Z state. During a WRITE cycle the input data
is masked. When DQMx is sampled HIGH and is an input mask signal for write
accesses and an output enable signal for read accesses. I/O0 through I/O7 are
controlled by DQM0. I/O8 throughI/O15 are controlled by DQM1. I/O16 through I/
O23 are controlled by DQM2. I/O24 through I/O31 are controlled by DQM3.
RAS, in conjunction with CAS and WE, forms the device command. See the
"Command Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the
"Command Truth Table" item for details on device commands.
VCCQ is the output buffer power supply.
VCC is the device internal power supply.
GNDQ is the output buffer ground.
GND is the device internal ground.
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
ADVANCE INFORMATION Rev. 00B
09/21/01
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