EDD5104ABTA 데이터 시트보기 (PDF) - Elpida Memory, Inc

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EDD5104ABTA

512M bits DDR SDRAM

Elpida Memory, Inc 

EDD5104ABTA, EDD5108ABTA

Pin Function

CK, /CK (input pins)

The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point

of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point

of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the

VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock

input to this pin. The other input signals are referred at CK rising edge.

/CS (input pin)

When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal

operations (bank active, burst operations, etc.) are held.

/RAS, /CAS, and /WE (input pins)

These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.

See "Command operation".

A0 toA12 (input pins)

Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the

/CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0

to the A9, A11 and A12 at the cross point of the CK rising edge and the /CK falling edge in a read or a write

command cycle. This column address becomes the starting address of a burst operation.

[Address Pins Table]

Address (A0 to A12)

Part number

Row address

Column address

EDD5104AB

AX0 to AX12

AY0 to AY9, AY11, AY12

EDD5108AB

AX0 to AX12

AY0 to AY9, AY11,

A10 (AP) (input pin)

A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If

A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge

command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write

command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled.

BA0 and BA1 (input pins)

BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See

Bank Select Signal Table)

[Bank Select Signal Table]

BA0

BA1

Bank 0

L

L

Bank 1

H

L

Bank 2

L

H

Bank 3

H

H

Remark: H: VIH. L: VIL

Preliminary Data Sheet E0237E30 (Ver. 3.0)

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