EDD5104ABTA 데이터 시트보기 (PDF) - Elpida Memory, Inc
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EDD5104ABTA Datasheet PDF : 50 Pages
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EDD5104ABTA, EDD5108ABTA
Parameter
-6B
Symbol min.
-7A
max. min.
-7B
max
min.
max. Unit Notes
Address and control input setup time tIS
0.75
—
0.9
—
0.9
—
Address and control input hold time tIH
0.75
—
0.9
—
0.9
—
ns 8
Address and control input pulse
width
tIPW 2.2
Mode register set command cycle
time
tMRD 2
Active to Precharge command
period
tRAS 42
Active to Active/Auto refresh
command period
tRC 60
Auto refresh to Active/Auto refresh
command period
tRFC
72
—
2.2
—
2
120000 45
—
67.5
—
75
—
2.2
—
2
120000 45
—
67.5
—
75
—
ns 7
—
tCK
120000 ns
—
ns
—
ns
Active to Read/Write delay
tRCD 18
—
20
—
20
—
ns
Precharge to active command period tRP 18
—
20
—
20
—
ns
Active to Autoprecharge delay
tRAP tRCD min. —
tRCD min. —
tRCD min. —
ns
Active to active command period tRRD 12
—
15
—
15
—
ns
Write recovery time
tWR 15
—
15
—
15
—
ns
Auto precharge write recovery and
precharge time
Internal write to Read command
delay
tDAL
tWTR
(tWR/tCK)+
(tRP/tCK)
1
—
(tWR/tCK)+
(tRP/tCK)
—
1
—
(tWR/tCK)+
(tRP/tCK)
—
1
—
tCK 13
tCK
Average periodic refresh interval tREF —
7.8
—
7.8
—
7.8
µs
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter
definitions, see ‘Timing Waveforms’ section.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
13. tDAL = (tWR/tCK)+(tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,
tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)
tDAL = 5 clocks
Preliminary Data Sheet E0237E30 (Ver. 3.0)
7
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