M29F080D(2002) 데이터 시트보기 (PDF) - STMicroelectronics
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M29F080D Datasheet PDF : 36 Pages
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M29F080D
SUMMARY DESCRIPTION
The M29F080D is a 8 Mbit (1Mb x8) non-volatile
memory that can be read, erased and repro-
grammed. These operations can be performed us-
ing a single low voltage 5V supply. On power-up
the memory defaults to its Read mode where it can
be read in the same way as a ROM or EPROM.
The memory is divided into 16 uniform blocks of
64Kbytes (see Figure 5, Block Addresses) that
can be erased independently so it is possible to
preserve valid data while old data is erased.
Blocks can be protected in groups of 4 to prevent
accidental Program or Erase commands from
modifying the memory. Program and Erase com-
mands are written to the Command Interface of
the memory. An on-chip Program/Erase Controller
simplifies the process of programming or erasing
the memory by taking care of all of the special op-
erations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions identi-
fied. The command set required to control the
memory is consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP40 (10 x 20mm) and
SO44 packages. Access times of 55, 70 and 90ns
are available. The memory is supplied with all the
bits erased (set to ’1’).
Figure 2. Logic Diagram
VCC
20
A0-A19
W
E
G
RP
M29F080D
8
DQ0-DQ7
RB
Table 1. Signal Names
A0-A19
Address Inputs
DQ0-DQ7 Data Inputs/Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
RB
Ready/Busy Output
VCC
Supply Voltage
VSS
Ground
NC
Not Connected Internally
VSS
AI06141
5/36
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