M32000D4AFP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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M32000D4AFP

SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

M32000D4AFP

SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER

PIN DESCRIPTION (2/3)

type

bus

control

pin name

SID

name

space

identifier

____ ____

BCH, BCL

byte control

I/O

output

(Hi-z)*

I/O

(Hi-z)*

__

BS

bus start

ST

bus status

__

R/W

______

BURST

read/write

burst

output

(Hi-z)*

output

(Hi-z)*

I/O

(Hi-z)*

output

(Hi-z)*

* (Hi-z): This pin goes to high-impedance in the hold state.

function

Space identifier between user space and I/O space.

SID = "L": user space

SID = "H": I/O space

SID = undefined: when idle

_In_d_i_cates the valid byte positions of transferred__d_a_ta.

BCH corresponds to the MSB side (D0 to D7), and BCL corresp_ o_ n_ d_ s

to th_e_L_S_B side (D8 to D15). During a read bus cycle, both BCH

and BCL are an "L" level.

____

____

During a write bus cycle, either BCH and/or BCL is an "L" level

depending on the byte(s) to be written.

When accessing the internal DRAM from an external bus master,

the byte control signal is input from the system bus side.

__

When the M32000D4AFP drives an external bus cycle, BS goes

to an "L" level at _ th_e start of the bus cycle.

In burst transfer, BS goes to the "L" level for each transfer

cycle. When accessing internal__resources such as an internal

DRAM or internal I/O register, BS is not output.

Indicates whether the bus cycle that the M32000D4AFP drives is

an instruction fetch access cycle or an operand access cycle.

ST = "L": for instruction fetch access

ST = "H": for operand access

ST = undefined: when idle

__

Outputs R/W to identify whether the external bus cycle a read or

a write cycle. W_h_en accessing the internal DRAM from an external

bus master, R/W is input from the external bus.

The M32000D4AFP drives two consecutive bus cycles to access

32-bit data allocated on the 32-bit word boundary.

For instruction fetches, it drives 8 (max.) consecutive cycles

(8 cycles in instruction cache mode) to da_ta__o_n_t_he 128-bit boundary.

During these consecutive bus cycles, BURST goes to "L" level.

When accessing 32-bit data, an "L" level followed by an "H" level

is output from address A30, because the MSB-side 16 bits are

accessed prior to the LSB-side 16 bits.

When accessing 128-bit data, the addresses are output from an

arbitrary 16-bit aligned address and wraparound within a 128-bit

aligned boundary.

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