M41T00SM6E 데이터 시트보기 (PDF) - STMicroelectronics

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M41T00SM6E

Serial access real-time clock

STMicroelectronics 

M41T00S

Operation

2.4

Data retention mode

With valid VCC applied, the M41T00S can be accessed as described above with READ or

WRITE cycles. Should the supply voltage decay, the power input will be switched from the

VCC pin to the battery when VCC falls below the battery backup switchover voltage (VSO). At

this time the clock registers will be maintained by the attached battery supply. On power-up,

when VCC returns to a nominal value, write protection continues for tREC.

For a further, more detailed review of lifetime calculations, please see Application Note

AN1012.

Figure 9. WRITE mode sequence

BUS ACTIVITY:

MASTER

SDA LINE

S

BUS ACTIVITY:

SLAVE

ADDRESS

WORD

ADDRESS (An)

DATA n

DATA n+1

DATA n+X P

AI00591

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