M48T36 데이터 시트보기 (PDF) - STMicroelectronics

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M48T36

CMOS 32K x 8 TIMEKEEPER SRAM

STMicroelectronics 

M48T36

When reset to a ’0’, the M48T36 oscillator starts

within 1 second.

Calibrating the Clock

The M48T36 is driven by a quartz controlled oscil-

lator with a nominal frequency of 32,768 Hz. The

devices are tested not to exceed 35 PPM (parts per

million) oscillator frequency error at 25°C, which

equates to about ± 1.53 minutes per month. With

the calibration bits properly set, the accuracy of

each M48T36 improves to better than ±4 PPM at

25°C.

Of course the oscillation rate of any crystal changes

with temperature. Most clock chips compensate for

crystal frequency and temperature shift error with

cumbersome trim capacitors. The M48T36 design,

however, employs periodic counter correction. The

calibration circuit adds or subtracts counts from the

oscillator divider circuit at the divide by 128 stage,

as shown in Figure 9. The number of times pulses

are blanked (subtracted, negative calibration) or

split (added, positive calibration) depends upon the

value loaded into the five bit Calibration byte found

in the Control Register. Adding counts speeds the

clock up, subtracting counts slows the clock down.

The Calibration byte occupies the five lower order

bits (D4-D0) in the Control Register 7FF8h. These

bits can be set to represent any value between 0

and 31 in binary form. Bit D5 is a Sign bit; ’1’

indicates positive calibration, ’0’ indicates negative

calibration. Calibration occurs within a 64 minute

cycle. The first 62 minutes in the cycle may, once

per minute, have one second either shortened by

128 or lengthened by 256 oscillator cycles. If a

binary ’1’ is loaded into the register, only the first 2

minutes in the 64 minute cycle will be modified; if a

binary 6 is loaded, the first 12 will be affected, and

so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 oscillator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or -2.034 PPM of adjustment per calibration

step in the calibration register. Assuming that the

oscillator is in fact running at exactly 32,768 Hz,

each of the 31 increments in the Calibration byte

would represent +10.7 or - 5.35 seconds per month

which corresponds to a total range of +5.5 or - 2.75

minutes per month.

Two methods are available for ascertaining how

much calibration a given M48T36 may require. The

first involves simply setting the clock, letting it run

for a month and comparing it to a known accurate

reference (like WWV broadcasts). While that may

seem crude, it allows the designer to give the end

user the ability to calibrate his clock as his environ-

ment may require, even after the final product is

packaged in a non-user serviceable enclosure. All

the designerhas to do is provide a simple utility that

accesses the Calibration byte. The utility could

even be menu driven and made foolproof.

The second approach is better suited to a manu-

facturing environment, and involves the use of the

IRQ/FT pin. The pin will toggle at 512Hz when the

Stop bit (D7 of 7FF9h) is ’0’, the FT bit (D6 of

7FFCh) is ’1’, the AFE bit (D7 of 7FF6h) is ’0’, and

the Watchdog Steering bit (D7 of 7FF7h) is ’1’ or

the Watchdog Register is reset (7FF7h = 0).

Any deviation from 512 Hz indicates the degree and

direction of oscillator frequency shift at the test

temperature. For example, a reading of 512.01024

Hz would indicate a +20 PPM oscillator frequency

error, requiring a -10(001010) to be loaded into the

Calibration Byte for correction. Note that setting or

changing the Calibration Byte does not affect the

Frequency test output frequency.

Figure 9. Clock Calibration

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

AI00594

11/17

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