M48T36 데이터 시트보기 (PDF) - STMicroelectronics
부품명
상세내역
제조사
M48T36 Datasheet PDF : 17 Pages
| |||
M48T36
READ MODE (cont’d)
valid data will be available after the latter of the Chip
Enable Access Time (tELQV) or Output Enable Ac-
cess Time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated
before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the AddressInputs
are changed while E and G remain active, output
data will remain valid for tAXQX (Output Data Hold
Time) but will go indeterminate until the next Ad-
dress Access.
WRITE MODE
The M48T36 is in the Write Mode whenever W and
E are low. The start of a write is referencedfrom the
latter occurring falling edge of W or E. A write is
terminated by the earlier rising edge of W or E. The
addresses must be held valid throughoutthe cycle.
E or W must returnhigh for a minimumof tEHAX from
Chip Enable or tWHAX from Write Enable prior to the
initiation of another read or write cycle. Data-in
must be valid tDVWH prior to the end of write and
remain valid for tWHDX afterward. G should be kept
high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on E and G a low on W will disable the outputs
tWLQZ after W falls.
DATA RETENTION MODE
With valid VCC applied, the M48T36 operates as a
conventional BYTEWIDE static RAM. Should the
supply voltage decay, the RAM will automatically
power-fail deselect,write protecting itself when VCC
falls within the VPFD(max), VPFD(min) window. All
outputs become high impedance, and all inputs are
treated as ”don’t care.”
Note: A power failure during a write cycle may
corrupt data at the currently addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below VPFD(min), the user can be as-
sured the memory will be in a write protected state,
provided the VCC fall time is not less than tF. The
M48T36 may respond to transient noise spikes on
VCC that reach into the deselect window during the
time the device is sampling VCC. Therefore, decou-
pling of the power supply lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T36 for an
accumulated period of at least 7 years when VCC is
less than VSO. As system power returns and VCC
rises above VSO, the battery is disconnected, and
the power supply is switched to external VCC. De-
select continues for tREC a f t e r VCC reaches
VPFD(max).
POWER-ON RESET
The M48T36 continuously monitors VCC. When
VCC falls to the power fail detect trip point, the RST
pulls low (open drain) and remains low on power-up
for 40ms to 200ms after VCC passes VPFD. A 1kΩ
resistor is recommended in order to control the rise
time. The reset pulse remains active with VCC at
VSS.
PROGRAMMABLE INTERRUPTS
The M48T36 has two programmable interrupts: an
alarm and a watchdog. When an interrupt condition
occurs, the M48T36 sets the appropriate flag bit in
the flag register 7FF0h. The interrupt enable bits in
7FF6h and the WDS (Watchdog Steering) bit in
7FF7h allow the interruptto activate the IRQ/FT pin.
The interrupt flags and the IRQ/FT output are
cleared by a read to the flags register. An interrupt
condition reset will not occur unless the addresses
are stable at the flag location for at least 15ns while
the device is in the read mode as shown in Figure
10.
The IRQ/FT pin is an open drain output and re-
quires a pull-up resistor. The pin remains in the high
impedance state unless an interrupt occurs or the
frequency test mode is enabled.
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data
registers, and not the actual clock counters, updat-
ing the registers can be halted without disturbing
the clock itself.
9/17
Share Link: 