M56692FP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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M56692FP Datasheet PDF : 5 Pages
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MITSUBISHI <CONTROL / DRIVER IC>
M56692FP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
FUNCTION
The M56692FP comprises a 32 bit bidirectional shift register, a 32
bit latch, and a parallel output HVO 1 – HVO32 connected to its
output.
In accordance with truth table 1, the data transfer direction of shift
register depends upon F/R input, and F/R being at “H” or open
allows pin 9 to turn to SIN and pin 2 to turn to SOUT, and F/R
being at “L” allows pin 2 to turn to SIN and pin 9 to turn to SOUT,
permitting data transfer from SIN to SOUT, respectively.
Inputting data to SIN and clock pulse to CLK allows SIN signal to
be put into the internal shift register when the clock changes from
“H” to “L”, and shift register data to be shifted sequentially.
Serial-output SOUT is used by connecting to the next stage
M56692FP SIN when more than one M56692FP is used to expand
bits in the series.
In accordance with truth table 2, parallel output allows the latch to
pass data through if LAT input is turned to “H”, and data to be
retained if LAT input is turned to “L”. Driver output HVOn allows
data from the latch to be output if BLK input is turned to “L”, and “L”
to be output if BLK input is turned to “H” irrespective of data from
the latch.
TRUTH TABLE
Truth table 1. Shift register section
Input
Input/output
F/R
CLK
SIN(SOUT)
SOUT(SIN)
H
↓
IN
OUT
H
H or L
L
↓
IN
OUT
OUT
IN
L
H or L
OUT
IN
Truth table 2. Latch and driver sections
Dn
LAT
BLK
HVOn
X
X
H
Output all “L”
H
H
L
H
L
H
L
L
X
L
L
Latch’s data output.
Shift register
DATA is shifted.
No changes.
DATA is shifted.
No changes.
Dn=nth bit DFF retention data
HVOn=nth bit driver output
L = “L” level
H = “H” level
X = “L” level or “H” level
PIN FUNCTION DESCRIPTION
Pin name
VDD
LGND
VH
PGND
CLK
SIN
SOUT
LAT
BLK
F/R
HVO1–32
Logic stage supply voltage
Function
Logic stage ground
Output stage supply voltage
Output stage supply ground
Clock input for the internal shift resister. The data enter the internal shift resisters and the data in the shift registers will be
shifted in order by High to Low change of the clock.
Serial data input
Serial data output
Latch input. When the LATCH is set to “H”, the data in the shift resister will enter the each latch circuit.
When the LATCH input is set to “L”, the data will be held.
Enable input for output control. When the BLK input is set to “L”, data in the latch circuit will appear at outputs.
When the BLK input is set to “H”, all outputs will be set to “L”.
Direction Control for the internal shift resister
Output driver (push-pull)
ABSOLUTE MAXIMUM RATINGS (Ta=25°C, unless otherwise noted)
Symbol
VDD
VH
VI
VO
VHVO
Pd
Tstg
Parameter
Logic stage supply voltage
Output stage supply voltage
Logic inputs voltage
Logic output voltage
Output voltage
Power dissipation range
Storage temperature range
Conditions
Data output
High supply voltage output pin
Ta ≤ 25°C
Ratings
Unit
-0.3 – 7
V
-0.3 – 90
V
-0.3 – VDD+0.3
V
-0.3 – VDD+0.3
V
-0.3 – VH
V
850
mW
-55 – 150
°C
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