M5M5256RV-55LL-I 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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M5M5256RV-55LL-I Datasheet PDF : 7 Pages
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'97.4.7
MITSUBISHI LSIs
M5M5256DP,KP,FP,VP,RV -45LL-I,-55LL-I,-70LL-I,
-45XL-I,-55XL-I,-70XL-I
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle ( /S control mode)
tCW
A0~14
/S
/W
DQ1~8
tsu (A)
tsu (S)
trec (W)
(Note 5)
(Note 3)
(Note 4)
tsu (D) th (D)
DATA IN
STABLE
(Note 3)
Note 3 : Hatching indicates the state is "don't care".
4 : Writing is executed in overlap of /S and /W low.
5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state.
6 : Don't apply inverted phase signal externally when DQ pin is output mode.
7 : ten, tdis are periodically sampled and are not 100% tested.
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