M5M532R16JTP-15 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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M5M532R16JTP-15 Datasheet PDF : 8 Pages
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MITSUBISHI LSIs
M5M532R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
Read cycle 4 (Note 7)
VIH
/UB,/LB
VIL
t CR
ta (B)
(Note 5)
tdis (B)
(Note 5) ten (B)
DQ1~16 VOH
VOL
/W=H /OE=L
/S=L
UNKNOWN
DATA VALID
Note 7. Addresses , /S and /OE valid prior to /LB,/UB transition low by (ta(A)-ta(B)), (ta(S)-ta(B)), (ta(OE)-ta(B)).
Write cycle (/W control mode)
A 0~14
/S
/OE
VIH
VIL
VIH
VIL
(Note8)
VIH
VIL
t CW
tsu (S)
tsu (A-WH)
tsu (A)
tw (W)
trec (W)
(Note8)
/W
/LB,/UB
VIH
VIL
VIH
VIL
(Note8)
tsu (B)
(Note8)
DQ1~16
VIH
VIL
(Input Data)
DQ1~16
VOH
(Output Data)
VOL
tdis (OE)
tdis (OE)
tsu(D) th(D)
DATA STABLE
tdis(W) (Note 5)
ten (OE) (Note 5)
ten (W)
Hi-Z
Note 8: Hatching indicates the state is don't care.
9: When the falling edge of /W is simultaneous or prior to the falling edge of /S, the output is maintained in the high impedance.
10: ten,tdis are periodically sampled and are not 100% tested.
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