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M5M5V108DKV-70H 데이터 시트보기 (PDF) - Renesas Electronics

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M5M5V108DKV-70H
Renesas
Renesas Electronics Renesas
M5M5V108DKV-70H Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
7th.July.2000 Ver. 1.1
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
VCC ................................. 2.7~3.6V
Input pulse level ............. VIH=2.2V,VIL=0.4V
Input rise and fall time ..... 5ns
Reference level ...............VOH=VOL=1.5V
Output loads ................... Fig.1, CL=30pF
CL=5pF (for ten,tdis)
Transition is measured ± 500mV from steady
state voltage. (for ten,tdis)
1TTL
DQ
CL
including
scope and JIG
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S1)
ta(S2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(OE)
ten(S1)
ten(S2)
ten(OE)
tV(A)
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S1 high
Output disable time after S2 low
Output disable time after OE high
Output enable time after S1 low
Output enable time after S2 high
Output enable time after OE low
Data valid time after address
(3) WRITE CYCLE
Symbol
Parameter
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(S1)
tsu(S2)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
Limits
-70H
Unit
Min Max
70
ns
70
ns
70
ns
70
ns
35
ns
25
ns
25
ns
25
ns
10
ns
10
ns
5
ns
10
ns
Limits
-70H
Unit
Min Max
70
ns
55
ns
0
ns
65
ns
65
ns
65
ns
30
ns
0
ns
0
ns
25
ns
25
ns
5
ns
5
ns
4

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