M5M5Y5672TG-25 데이터 시트보기 (PDF) - Mitsumi

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M5M5Y5672TG-25

18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

Mitsumi 

MITSUBISHI LSIs

M5M5Y5672TG – 25,22,20

18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

Echo Clock Control in Two Banks

CLK

ADD

A

B

C

D

E

F

E1#

E2# Bank1

E2 Bank2

DQ

Bank1

CQ

Bank1

CQ Bank1

+ CQ Bank2

CQ

Bank2

DQ

Bank2

Q(A)

Q(C)

Q(B)

Q(D)

Note9. E1# does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously

deselected by E2 or E3 being sampled false.

It should be noted that deselection of the SRAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of

Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the SRAM via E1# does not deactivate the

Echo Clocks.

10

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ELECTRIC

M5M5Y5672TG REV.0.1

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