M5M5Y5636TG-20 데이터 시트보기 (PDF) - Renesas Electronics

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M5M5Y5636TG-20

18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

Renesas Electronics 

MITSUBISHI LSIs

M5M5Y5636TG – 25,22,20

18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

Write Operation

Double Late Write

Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and E3)

are active and the write enable input signal (W#) is asserted low.

Double Late Write means that Data In is required on the third rising edge of clock. It is designed to eliminate dead bus cycles when

turning the bus around between reads and writes, or writes and reads.

CLK

E1#

ADV

W#

BWx#

ADD

DQ

CQ

A

Read A

B

Write B

C

Q(A)

Read C

D

D(B)

E

Q(C)

F

D(D)

Write D

Read E

Read F

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Preliminary

M5M5Y5636TG REV.0.6

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