M5M5Y5636TG-20 데이터 시트보기 (PDF) - Renesas Electronics

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M5M5Y5636TG-20

18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

Renesas Electronics 

MITSUBISHI LSIs

M5M5Y5636TG – 25,22,20

18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

DC OPERATED TRUTH TABLE

Name

Input Status

Operation

LBO#

HIGH or NC

LOW

Interleaved Burst Sequence

Linear Burst Sequence

Note5. LBO# is DC operated pin.

Note6. NC means No Connection.

Note7. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.

BURST SEQUENCE TABLE

(1) Interleaved Burst Sequence (when LBO# = HIGH or NC)

Operation

A18~A2

First access, latch external address

A18~A2

Second access(first burst address)

latched A18~A2

Third access(second burst address)

latched A18~A2

Fourth access(third burst address)

latched A18~A2

A1,A0

0,0

0,1

1,0

1,1

0,1

0,0

1,1

1,0

1,0

1,1

0,0

0,1

1,1

1,0

0,1

0,0

(2) Linear Burst Sequence (when LBO# = LOW)

Operation

A18~A2

First access, latch external address

A18~A2

Second access(first burst address)

latched A18~A2

Third access(second burst address)

latched A18~A2

Fourth access(third burst address)

latched A18~A2

Note8. The burst sequence wraps around to its initial state upon completion.

A1,A0

0,0

0,1

1,0

1,1

0,1

1,0

1,1

0,0

1,0

1,1

0,0

0,1

1,1

0,0

0,1

1,0

8/29

Preliminary

M5M5Y5636TG REV.0.6

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