MC80C86 데이터 시트보기 (PDF) - Intel

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MC80C86

16-BIT CHMOS MICROPROCESSOR

Intel 

M80C86 M80C86-2

Table 1 Pin Description

The following pin function descriptions are for M80C86 systems in either minimum or maximum mode The

‘‘Local Bus’’ in these descriptions is the direct multiplexed bus interface connection to the M80C86 (without

regard to additional bus buffers)

Symbol

AD15 – AD0

A19 S6

A18 S5

A17 S4

A16 S3

Pin No

2– 16 39

35– 38

Type

IO

O

Name and Function

ADDRESS DATA BUS These lines constitute the time multiplexed

memory IO address (T1) and data (T2 T3 TW T4) bus A0 is

analogous to BHE for the lower byte of the data bus pins D7 – D0 It

is LOW during T1 when a byte is to be transferred on the lower

portion of the bus in memory or I O operations Eight-bit oriented

devices tied to the lower half would normally use A0 to condition

chip select functions (See BHE ) These lines are active HIGH and

float to 3-state OFF(1) during interrupt acknowledge and local bus

‘‘hold acknowledge ’’

ADDRESS STATUS During T1 these are the four most significant

address lines for memory operations During I O operations

these lines are LOW During memory and I O operations

status information is available on these lines during T2 T3 TW

and T4 The status of the interrupt enable FLAG bit (S5) is updated

at the beginning of each CLK cycle A17 S4 and A16 S3 are

encoded as shown

This information indicates which relocation register is presently

being used for data accessing

These lines float to 3-state OFF(1) during local bus ‘‘hold

acknowledge ’’

BHE S7

A17 S4

0 (LOW)

0

1 (HIGH)

1

S6 is 0

(LOW)

A16 S3

0

1

0

1

Characteristics

Alternate Data

Stack

Code or None

Data

34

O BUS HIGH ENABLE STATUS During T1 the bus high enable signal

(BHE) should be used to enable data onto the most significant half

of the data bus pins D15 – D8 Eight-bit oriented devices tied to the

upper half of the bus would normally use BHE to condition chip

select functions BHE is LOW during T1 for read write and interrupt

acknowledge cycles when a byte is to be transferred on the high

portion of the bus The S7 status information is available during T2

T3 and T4 The signal is active LOW and floats to 3-state OFF(1) in

‘‘hold ’’ It is LOW during T1 for the first interrupt acknowledge cycle

BHE

A0

0

0

0

1

1

0

1

1

Characteristics

Whole word

Upper byte from

to odd address

Lower byte from

to even address

None

2

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