M88 데이터 시트보기 (PDF) - STMicroelectronics

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M88

In-System Programmable (ISP) Multiple-Memory and Logic FLASH+PSD Systems (with CPLD) for MCUs

STMicroelectronics 

M88 FAMILY

In-System Programmable (ISP) Multiple-Memory and

Logic FLASH+PSD Systems (with CPLD) for MCUs

DATA BRIEFING

s Single Supply Voltage:

– 5 V±10% for M88xxFxY

– 3 V (+20/–10%) for M88xxFxW

s 1 or 2 Mbit of Primary Flash Memory (8 uniform

sectors, 16K x 8, or 32K x 8)

s A second non-volatile memory:

– 256 Kbit (32K x 8) EEPROM (for M8813F1x)

or Flash memory (for M88x3F2x)

– 4 uniform sectors (8K x 8)

s SRAM (16 Kbit, 2K x 8; or 64 Kbit, 8K x 8)

s Over 3,000 Gates of PLD: DPLD and CPLD

s 27 Reconfigurable I/O ports

s Enhanced JTAG Serial Port

s Programmable power management

s Stand-by current:

– 50 µA for M88xxFxY

– 25 µA for M88xxFxW

s High Endurance:

– 100,000 Erase/Write Cycles of Flash Memory

– 10,000 Erase/Write Cycles of EEPROM

– 1,000 Erase/Write Cycles of PLD

DESCRIPTION

The FLASH+PSD family of memory systems for

microcontrollers (MCUs) brings In-System-

Table 1. Signal Names

PA0-PA7

Port-A

PB0-PB7

Port-B

PC0-PC7

Port-C

PC2 = Voltage Stand-by

PD0-PD2

AD0-AD15

Port-D

Address/Data

CNTL0-CNTL2

RESET

Control

Reset

VCC

Supply Voltage

VSS

Ground

PQFP52 (T)

PLCC52 (K)

Figure 1. Logic Diagram

VCC

8

PA0-PA7

3

CNTL0-

CNTL2

16

AD0-AD15

FLASH+PSD

8

PB0-PB7

8

PC0-PC7

RESET

3

PD0-PD2

VSS

AI02856

June 2000

1/7

Complete data available on Data-on-Disc CD-ROM or at www.st.com

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