M95040-SBN3T 데이터 시트보기 (PDF) - STMicroelectronics

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M95040-SBN3T

4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock

STMicroelectronics 

Figure 11. Write Status Register (WRSR) Sequence

M95040, M95020, M95010

S

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

C

Instruction

Status

Register In

D

76543210

High Impedance

MSB

Q

AI01445B

Write Status Register (WRSR)

This instruction has no effect on bits b7, b6, b5, b4,

b1 and b0 of the Status Register.

As shown in Figure 11, to send this instruction to

the device, Chip Select (S) is first driven Low. The

bits of the instruction byte and data byte are then

shifted in on Serial Data Input (D).

The instruction is terminated by driving Chip Se-

lect (S) High. Chip Select (S) must be driven High

after the rising edge of Serial Clock (C) that latch-

es the eighth bit of the data byte, and before the

the next rising edge of Serial Clock (C). If this con-

dition is not met, the Write Status Register

(WRSR) instruction is not executed. The self-

timed Write Cycle starts, and continues for a peri-

od tW (as specified in Tables 17 to 20), at the end

of which the Write in Progress (WIP) bit is reset to

0.

The instruction is not accepted, and is not execut-

ed, under the following conditions:

– if the Write Enable Latch (WEL) bit has not been

set to 1 (by executing a Write Enable instruction

just before)

– if a Write Cycle is already in progress

– if the device has not been deselected, by Chip

Select (S) being driven High, after the eighth bit,

b0, of the data byte has been latched in

– if Write Protect (W) is Low.

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