MAX11047ETN 데이터 시트보기 (PDF) - Maxim Integrated
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MAX11047ETN Datasheet PDF : 25 Pages
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4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Pin Description
PIN
MAX11047 MAX11048 MAX11049
(TQFN-EP) (TQFN-EP) (TQFN-EP)
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7, 21, 50 7, 21, 50 7, 21, 50
8, 20, 51
9
8, 20, 51
9
8, 20, 51
9
10
10
10
11
11
11
12
12
12
13
13
13
14
14
14
15
15
15
16
16
16
17
17
17
18
18
18
19
19
19
22, 28, 35, 22, 28, 35, 22, 28, 35,
43, 49
43, 49
43, 49
23, 27, 33,
38, 44, 48
24, 30,
41, 47
25, 31,
40, 46
26, 29,
42, 45
32
34
23, 27, 33,
38, 44, 48
24, 30,
41, 47
25, 31,
40, 46
26, 45
29
32
23, 27, 33,
38, 44, 48
24, 30,
41, 47
25, 31,
40, 46
—
26
29
36
36
36
NAME
DB13
DB12
DB11
DB10
DB9
DB8
DGND
DVDD
DB7
DB6
DB5
DB4
DB3/CR3
DB2/CR2
DB1/CR1
DB0/CR0
EOC
CONVST
SHDN
RDC
AGNDS
AVDD
AGND
I.C.
CH0
CH1
REFIO
FUNCTION
16-Bit Parallel Data Bus Digital Output Bit 13
16-Bit Parallel Data Bus Digital Output Bit 12
16-Bit Parallel Data Bus Digital Output Bit 11
16-Bit Parallel Data Bus Digital Output Bit 10
16-Bit Parallel Data Bus Digital Output Bit 9
16-Bit Parallel Data Bus Digital Output Bit 8
Digital Ground
Digital Supply. Bypass to DGND with a 0.1µF capacitor at each DVDD input.
16-Bit Parallel Data Bus Digital Output Bit 7
16-Bit Parallel Data Bus Digital Output Bit 6
16-Bit Parallel Data Bus Digital Output Bit 5
16-Bit Parallel Data Bus Digital Output Bit 4
16-Bit Parallel Data Bus Digital Output Bit 3/Configuration Register Input Bit 3
16-Bit Parallel Data Bus Digital Output Bit 2/Configuration Register Input Bit 2
16-Bit Parallel Data Bus Digital Output Bit 1/Configuration Register Input Bit 1
16-Bit Parallel Data Bus Digital Output Bit 0/Configuration Register Input Bit 0
Active-Low End of Conversion Output. EOC goes low when conversion is
completed. EOC goes high when a conversion is initiated.
Convert Start Input. Rising edge of CONVST ends sample and starts a
conversion on the captured sample. The ADC is in acquisition mode when
CONVST is low and CONVST mode = 0.
Shutdown Input. If SHDN is held high, the entire device enters and stays in a
low-current state. Contents of the Configuration register are not lost when in
the shutdown state.
Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to
AGND with at least an 80µF total capacitance. See the Layout, Grounding,
and Bypassing section.
Signal Ground. Connect all AGND and AGNDS inputs together on PWB.
Analog Supply Input. Bypass AVDD to AGND with a 0.1µF capacitor at each
AVDD input.
Analog Ground. Connect all AGND inputs together.
Internally Connected. Connect to AGND
Channel 0 Analog Input
Channel 1 Analog Input
External Reference Input/Internal Reference Output. Place a 0.1µF capacitor
from REFIO to AGND.
10 ______________________________________________________________________________________
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