SY10EL34LZC(1998) 데이터 시트보기 (PDF) - Micrel

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SY10EL34LZC
(Rev.:1998)

5V/3.3V ÷2, ÷4, ÷8 CLOCK GENERATION CHIP

Micrel 

Micrel

TIMING DIAGRAM

ClockWorks™

SY10EL34/L

SY100EL34/L

Internal Clock

Disabled

Internal Clock

Enabled

CLK

Q0

Q1

Q2

EN

The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers

will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs

will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted.

PRODUCT ORDERING CODE

3.3V

Ordering

Code

SY10EL34LZC

Package

Type

Z16-2

Operating

Range

Commercial

SY10EL34LZCTR

Z16-2 Commercial

SY100EL34LZC

Z16-2 Commercial

SY100EL34LZCTR Z16-2 Commercial

VEE Range

(V)

-3.0 to -3.8

-3.0 to -3.8

-3.0 to -3.8

-3.0 to -3.8

5V

Ordering

Code

SY10EL34ZC

SY10EL34ZCTR

SY100EL34ZC

SY100EL34ZCTR

Package

Type

Z16-2

Z16-2

Z16-2

Z16-2

Operating

Range

Commercial

Commercial

Commercial

Commercial

VEE Range

(V)

-4.75 to -5.5

-4.75 to -5.5

-4.2 to -5.5

-4.2 to -5.5

3

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